POWER TRANSISTOR WITH METAL SOURCE AND METHOD OF MANUFACTURE

• US 20100059819A1
• Filed: 08/20/2009
• Published: 03/11/2010
• Est. Priority Date: 07/15/2004
• Status: Abandoned Application

• Current Assignee: Spinnaker Semiconductor, Inc.
• Original Assignee: Spinnaker Semiconductor, Inc.
• Inventors: Snyder, John P.
• Application Number:
  US12/545,057
• Publication Number:
  US 20100059819A1
• Time in Patent Office: Days
• US Class Current: 257/343
• CPC Class Codes: H01L 29/0839 Cathode regions of thyristors
• CPC Class Codes: H01L 29/1083 with an inactive supplementary region, e.g. for preventing punch-through, improving capacity effect or leakage current
• CPC Class Codes: H01L 29/41741 for vertical or pseudo-vertical devices
• CPC Class Codes: H01L 29/66643 with source or drain regions formed by a Schottky barrier or a conductor-insulator-semiconductor structure
• CPC Class Codes: H01L 29/7397 and a gate structure lying on a slanted or vertical surface or formed in a groove, e.g. trench gate IGBT
• CPC Class Codes: H01L 29/7802 Vertical DMOS transistors, i.e. VDMOS transistors
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236
• CPC Class Codes: H01L 29/7839 with Schottky drain or source contact
• CPC Class Codes: H01L 29/872 Schottky diodes

Abstract

A metal source power transistor device and method of manufacture is provided, wherein the metal source power transistor having a source which is comprised of metal and which forms a Schottky barrier with the body region and channel region of the transistor. The metal source power transistor is unconditionally immune from parasitic bipolar action and, therefore, the effects of snap-back and latch-up, without the need for a body contact. The ability to allow the body to float in the metal source power transistor reduces the process complexity and allows for more compact device layout.

Claims

1. A metal source power transistor comprising:

a semiconductor substrate forming a drain layer of a first conductivity type;

a drift layer of a similar first conductivity type arranged on said drain layer;

a body region of a second conductivity type arranged in said drift layer;

a source region arranged in said body region, wherein said source region is formed from a metal and forms a Schottky contact to said body region; and

a gate electrode arranged on said body region and said drift region.

2. The transistor of claim 1 wherein said drain layer is comprised of P+ silicon, said drift layer is comprised of epitaxially grown P-type silicon, said body region is comprised of N-type silicon, and said source region is formed of anyone or combination of Platinum Silicide, Palladium Silicide or Iridium Silicide.

3. The transistor of claim 1 wherein said metal source power transistor is a planar power MOS transistor.

4. A metal source power transistor comprising:

a semiconductor substrate forming a drain layer of a first conductivity type;

a drift layer of the first conductivity type arranged on the drain layer;

a body region of a second conductivity type arranged in the drift layer;

a source region arranged in the body region, wherein the source region includes at least one metal that forms a Schottky contact to the body region; and

a gate structure arranged on the body region.

5. The transistor of claim 4, wherein the drain layer includes P+ silicon, the drift layer includes epitaxially grown P-type silicon, the body region includes N-type silicon, and the source region includes Iridium Silicide.

6. The transistor of claim 4, wherein the semiconductor substrate includes silicon or silicon on insulator (SOI).

7. The transistor of claim 4, wherein the semiconductor substrate includes at least one selected from the group consisting of silicon germanium, silicon carbide, gallium arsenide, indium phosphide, and gallium nitride.

8. The transistor of claim 4, wherein the source region and the drift region are controllably electrically connected to one another by a channel region that is controlled by a voltage on the gate structure.

9. The transistor of claim 8, wherein the channel region is strained.

10. The transistor of claim 4, wherein the semiconductor substrate is strained.

11. The transistor of claim 4, wherein the gate structure includes:

a gate insulating layer that covers a common surface of both the drift layer and the body region;

a gate electrode that covers the gate insulating layer; and

an insulating sidewall spacer that covers at least one side of the gate electrode.

12. The transistor of claim 11, wherein the gate insulating layer includes silicon dioxide.

13. The transistor of claim 11, wherein the gate electrode includes Boron-doped poly silicon.

14. The transistor of claim 11, wherein the gate electrode includes a metal.

15. The transistor of claim 4, wherein the body region is not contacted by a body contact allowing the body region to electrically float.

16. The transistor of claim 4, further comprising an external protection diode electrically connected to at least one of the source region or the drain layer.

17. The transistor of claim 4, wherein the drain layer includes P+ silicon, the drift layer includes epitaxially grown P-type silicon, the body region includes N-type silicon, and the source region includes Palladium Silicide.

18. The transistor of claim 4, wherein the drain layer-includes P+ silicon, the drift layer—

includes epitaxially grown P-type silicon, the body region includes N-type silicon, and the source region includes Platinum Silicide.

19. The transistor of claim 4, wherein the gate structure is further arranged on the drift layer.

20. A planar metal source power transistor comprising:

a semiconductor substrate forming a drain layer, wherein the semiconductor substrate includes silicon and wherein the drain layer includes P+ silicon;

a drift layer arranged on the drain layer, wherein the drift layer includes epitaxially grown P-type silicon;

a body region arranged in the drift layer, wherein the body region includes N-type silicon;

a source region arranged in the body region, wherein the source region includes at least one metal that forms a Schottky contact to the body region and wherein the at least one metal includes platinum silicide;

a gate structure arranged on the body region and on the drain layer wherein the gate structure includes;

a gate insulating layer that covers a common surface of both the drift layer and the body region, wherein the gate insulating layer includes silicon dioxide;

a gate electrode that covers the gate insulating layer, wherein the gate electrode includes boron-doped polysilicon; and

an insulating sidewall spacer that covers at least one side of the gate electrode,

wherein the insulating sidewall spacer includes silicon dioxide;

wherein the source region and the drift region are controllably electrically connected to one another by a channel region that is controlled by a voltage on the gate structure; and

wherein the body region is not contacted by a body contact allowing the body region to electrically float.

21. The transistor of claim 20, wherein the at least one metal further includes iridium silicide.