Semiconductor Device and Method of Forming an IPD over a High-Resistivity Encapsulant Separated from other IPDS and Baseband Circuit

• US 20100059854A1
• Filed: 09/05/2008
• Published: 03/11/2010
• Est. Priority Date: 09/05/2008
• Status: Active Grant

• Current Assignee: Stats Chippac Pte. Ltd. (JCET Group Co., Ltd.)
• Original Assignee: Stats Chippac Limited
• Inventors: Chen, Kang, Fang, Jianmin, Lin, Yaojian, Cao, Haijing
• Granted Patent: US 8,263,437 B2
• Time in Patent Office: Days
• US Class Current: 257/528
• CPC Class Codes: H01L 21/568 Temporary substrate used as encapsulation process aid H01L21/4832 and H01L21/566 take precedence
• CPC Class Codes: H01L 21/6835 using temporarily an auxiliary support
• CPC Class Codes: H01L 2224/04042 Bonding areas specifically adapted for wire connectors, e.g. wirebond pads
• CPC Class Codes: H01L 2224/0554 External layer
• CPC Class Codes: H01L 2224/0555 Shape
• CPC Class Codes: H01L 2224/0556 Disposition
• CPC Class Codes: H01L 2224/0557 the external layer being disposed on a via connection of the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/05571 the external layer being disposed in a recess of the surface
• CPC Class Codes: H01L 2224/05573 Single external layer
• CPC Class Codes: H01L 2224/05599 Material
• CPC Class Codes: H01L 2224/05611 Tin [Sn] as principal constituent
• CPC Class Codes: H01L 2224/05624 Aluminium [Al] as principal constituent
• CPC Class Codes: H01L 2224/05639 Silver [Ag] as principal constituent
• CPC Class Codes: H01L 2224/05644 Gold [Au] as principal constituent
• CPC Class Codes: H01L 2224/05647 Copper [Cu] as principal constituent
• CPC Class Codes: H01L 2224/05655 Nickel [Ni] as principal constituent
• CPC Class Codes: H01L 2224/131 with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
• CPC Class Codes: H01L 2224/16225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/16227 the bump connector connecting to a bond pad of the item
• CPC Class Codes: H01L 2224/16235 the bump connector connecting to a via metallisation of the item
• CPC Class Codes: H01L 2224/48091 : Arched
• CPC Class Codes: H01L 2224/48247 : connecting the wire to a bond pad of the item
• CPC Class Codes: H01L 2224/73265 : Layer and wire connectors
• CPC Class Codes: H01L 2224/81001 : involving a temporary auxiliary member not forming part of the bonding apparatus
• CPC Class Codes: H01L 2224/81805 : involving forming a eutectic alloy at the bonding interface
• CPC Class Codes: H01L 23/5389 : the chips being integrally enclosed by the interconnect and support structures
• CPC Class Codes: H01L 24/03 : Manufacturing methods
• CPC Class Codes: H01L 24/05 : of an individual bonding area
• CPC Class Codes: H01L 24/16 : of an individual bump connector
• CPC Class Codes: H01L 24/81 : using a bump connector
• CPC Class Codes: H01L 25/03 : all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
• CPC Class Codes: H01L 25/16 : the devices being of types provided for in two or more different main groups of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. forming hybrid circuits
• CPC Class Codes: H01L 25/50 : Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00 H01L21/50 takes precedence
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00011 : Not relevant to the scope of the group, the symbol of which is combined with the symbol of this group
• CPC Class Codes: H01L 2924/00012 : Relevant to the scope of the group, the symbol of which is combined with the symbol of this group
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01029 : Copper [Cu]
• CPC Class Codes: H01L 2924/01078 : Platinum [Pt]
• CPC Class Codes: H01L 2924/01079 : Gold [Au]
• CPC Class Codes: H01L 2924/01322 : Eutectic Alloys, i.e. obtained by a liquid transforming into two solid phases
• CPC Class Codes: H01L 2924/014 : Solder alloys
• CPC Class Codes: H01L 2924/04941 : TiN
• CPC Class Codes: H01L 2924/09701 : Low temperature co-fired ceramic [LTCC]
• CPC Class Codes: H01L 2924/12041 : LED
• CPC Class Codes: H01L 2924/12042 : LASER
• CPC Class Codes: H01L 2924/13091 : Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]
• CPC Class Codes: H01L 2924/14 : Integrated circuits
• CPC Class Codes: H01L 2924/1433 : Application-specific integrated circuit [ASIC]
• CPC Class Codes: H01L 2924/15174 : in different layers of the multilayer substrate
• CPC Class Codes: H01L 2924/15184 : in different layers of the multilayer substrate
• CPC Class Codes: H01L 2924/15311 : being a ball array, e.g. BGA
• CPC Class Codes: H01L 2924/181 : Encapsulation
• CPC Class Codes: H01L 2924/19041 : being a capacitor
• CPC Class Codes: H01L 2924/19042 : being an inductor
• CPC Class Codes: H01L 2924/19043 : being a resistor
• CPC Class Codes: H01L 2924/19105 : in a side-by-side arrangement on a common die mounting substrate
• CPC Class Codes: H01L 2924/30105 : Capacitance

Abstract

A semiconductor device has a first conductive layer formed over a sacrificial substrate. A first integrated passive device (IPD) is formed in a first region over the first conductive layer. A conductive pillar is formed over the first conductive layer. A high-resistivity encapsulant greater than 1.0 kohm-cm is formed over the first IPD to a top surface of the conductive pillar. A second IPD is formed over the encapsulant. The first encapsulant has a thickness of at least 50 micrometers to vertically separate the first and second IPDs. An insulating layer is formed over the second IPD. The sacrificial substrate is removed and a second semiconductor die is disposed on the first conductive layer. A first semiconductor die is formed in a second region over the substrate. A second encapsulant is formed over the second semiconductor die and a thermally conductive layer is formed over the second encapsulant.

Claims

1. A method of manufacturing a semiconductor device, comprising:

providing a sacrificial substrate;

forming a first insulation layer over the sacrificial substrate;

forming a first conductive layer over the first insulating layer;

forming a first integrated passive device (IPD) in a first region over the first conductive layer;

forming a plurality of conductive pillars over the first conductive layer;

disposing a first semiconductor die in a second region over the sacrificial substrate, the second region being separate from the first region;

forming a first encapsulant over the first IPD to a top surface of the conductive pillars, the first encapsulant having a resistivity greater than 1.0 kohm-cm;

forming a second IPD over the first encapsulant;

forming a first insulating layer over the second IPD;

removing the sacrificial substrate; and

disposing a second semiconductor die over the first conductive layer.

2. The method of claim 1, wherein the first IPD is a capacitor or resistor and the second IPD is an inductor.

3. The method of claim 1, wherein the first encapsulant has a thickness of at least 50 micrometers to vertically separate the first and second IPDs.

4. The method of claim 1, wherein the first semiconductor die includes a digital circuit and the second semiconductor die includes a third IPD.

5. The method of claim 1, further including disposing a third semiconductor die over the first conductive layer in the second region, the third semiconductor die including a digital circuit.

6. The method of claim 1, further including:

forming a second encapsulant over the second semiconductor die; and

forming a thermally conductive layer over the second encapsulant.

7. The method of claim 6, further including forming a second insulating layer between the first encapsulant and second IPD.

8. A method of manufacturing a semiconductor device, comprising:

providing a sacrificial substrate;

forming a first conductive layer over the sacrificial substrate;

forming a first integrated passive device (IPD) in a first region over the first conductive layer;

forming a conductive pillar over the first conductive layer;

forming a high-resistivity encapsulant over the first IPD to a top surface of the conductive pillar; and

forming a second IPD over the high-resistivity encapsulant.

9. The method of claim 8, further including:

forming an insulating layer over the second IPD;

removing the sacrificial substrate; and

disposing a second semiconductor die over the first conductive layer.

10. The method of claim 8, further including forming a first semiconductor die in a second region over the sacrificial substrate, the second region being separate from the first region.

11. The method of claim 8, wherein the encapsulant has a resistivity greater than 1.0 kohm-cm.

12. The method of claim 8, wherein the first IPD is a capacitor or resistor and the second IPD is an inductor.

13. The method of claim 8, wherein the encapsulant has a thickness of at least 50 micrometers to vertically separate the first and second IPDs.

14. The method of claim 8, wherein the first semiconductor die includes a digital circuit and the second semiconductor die includes a third IPD.

15. The method of claim 8, further including:

forming a second encapsulant over the second semiconductor die; and

forming a thermally conductive layer over the second encapsulant.

16. A method of manufacturing a semiconductor device, comprising:

providing a substrate;

forming a first conductive layer over the substrate;

forming a first integrated passive device (IPD) over the first conductive layer;

forming a conductive pillar over the first conductive layer;

forming an encapsulant over the first IPD to a top surface of the conductive pillar; and

forming a second IPD over the encapsulant.

17. The method of claim 16, further including forming a first semiconductor die in a second region over the substrate, the second region being separate from the first region.

18. The method of claim 16, further including:

forming an insulating layer over the second IPD;

removing the substrate; and

disposing a second semiconductor die over the first conductive layer.

19. The method of claim 16, wherein the encapsulant has a resistivity greater than 1.0 kohm-cm.

20. The method of claim 16, wherein the encapsulant has a thickness of at least 50 micrometers to vertically separate the first and second IPDs.

21. A semiconductor device, comprising:

a substrate;

a first conductive layer formed over the substrate;

a first integrated passive device (IPD) formed in a first region over the first conductive layer;

a conductive pillar formed over the first conductive layer;

a high-resistivity encapsulant formed over the first IPD to a top surface of the conductive pillar; and

a second IPD formed over the high-resistivity encapsulant.

22. The semiconductor device of claim 21, further including a first semiconductor die formed in a second region over the substrate, the second region being separate from the first region.

23. The semiconductor device of claim 21, wherein the encapsulant has a resistivity greater than 1.0 kohm-cm.

24. The semiconductor device of claim 21, wherein the first IPD is a capacitor or resistor and the second IPD is an inductor.

25. The semiconductor device of claim 21, wherein the encapsulant has a thickness of at least 50 micrometers to vertically separate the first and second IPDs.