LOW LEAKAGE AND DATA RETENTION CIRCUITRY

• US 20100060319A1
• Filed: 08/17/2009
• Published: 03/11/2010
• Est. Priority Date: 02/19/2004
• Status: Active Grant

• Current Assignee: Mosaid Technologies Incorporated (MOSAID Technologies Inc. (f/k/a Conversant Intellectual Property Management))
• Original Assignee: Mosaid Technologies Incorporated (MOSAID Technologies Inc. (f/k/a Conversant Intellectual Property Management))
• Inventors: Cole, Andrew, Callahan, John M., Walker, William G., Zampaglione, Michael A., Hoberman, Barry A., Hillman, Daniel L.
• Granted Patent: US 7,940,081 B2
• Time in Patent Office: Days
• US Class Current: 326/68
• CPC Class Codes: G11C 5/14 Power supply arrangements , e.g. power down, chip selection or deselection, layout of wirings or power grids, or multiple supply levels
• CPC Class Codes: G11C 5/144 Detection of predetermined disconnection or reduction of power supply, e.g. power down or power standby
• CPC Class Codes: G11C 5/148 Details of power up or power down circuits, standby circuits or recovery circuits
• CPC Class Codes: H02M 3/07 using capacitors charged and discharged alternately by semiconductor devices with control electrode , e.g. charge pumps
• CPC Class Codes: H03K 17/102 in field-effect transistor switches
• CPC Class Codes: H03K 19/0016 by using a control or a clock signal, e.g. in order to apply power supply
• CPC Class Codes: H03K 19/00315 in field-effect transistor circuits
• CPC Class Codes: H03K 3/0372 of the master-slave type
• CPC Class Codes: H03K 3/356086 with additional means for controlling the main nodes H03K3/356104, H03K3/3562 take precedence
• CPC Class Codes: H03K 3/356113 using additional transistors in the input circuit
• CPC Class Codes: H03K 5/14 by the use of delay lines H03K5/133 takes precedence

Abstract

An integrated circuit includes first circuitry and sleep transistor circuitry. The first circuitry receives input signals and processes the input signals. The first circuitry also retains data in a sleep state that has low leakage. The sleep transistor circuitry is coupled to the first circuitry and receives a sleep signal that has a negative voltage. The sleep circuitry reduces power consumption of the first circuitry in the sleep state to have low leakage based on the sleep signal while retaining the data in the first circuitry.

Claims

1-63. -63. (canceled)

64. An integrated circuit comprising:

two power supply terminals for powering of the integrated circuit, said power supply terminals including a V_dd positive supply terminal and a V_ss ground terminal together defining a range of logic levels;

cells in series with a sleep transistor electrically connected to one of said power supply terminals, each of said cells being either a logic gate or a storage cell;

generator circuitry configured to generate a variable voltage outside said range of logic levels; and

additional circuitry configured to apply, in a power down mode, said variable voltage to said sleep transistor.

65. The integrated circuit as claimed in claim 64 wherein said one of the power supply terminals is the V_ss terminal, said variable voltage outside the range of logic levels is a voltage lower than V_ss, and said sleep transistor is an n-channel transistor.

66. The integrated circuit as claimed in claim 65 wherein said additional circuitry applies V_dd to said sleep transistor when in another mode than said power down mode.

67. The integrated circuit as claimed in claim 65 wherein said additional circuitry applies a voltage greater than V_dd to said sleep transistor when in another mode than said power down mode.

68. The integrated circuit as claimed in claim 64 wherein said one of the power supply terminals is the V_dd terminal, said variable voltage is a voltage higher than V_dd, and said sleep transistor is a p-channel transistor.

69. The integrated circuit as claimed in claim 68 wherein said additional circuitry applies V_ss to said sleep transistor when not in a power down mode.

70. The integrated circuit as claimed in claim 68 wherein said additional circuitry applies a voltage less than V_ss to said sleep transistor when not in a power down mode.

71. The integrated circuit as claimed in claim 64 wherein said cells include inverters.

72. The integrated circuit as claimed in claim 64 wherein said cells include flip-flops.

73. The integrated circuit as claimed in claim 64 wherein said sleep transistor has a similar gate thickness as transistors in said cells.

74. The integrated circuit as claimed in claim 73 wherein said sleep transistor and said transistors in said cells are thin gate devices.

75. The integrated circuit as claimed in claim 64 wherein said additional circuitry applies the voltage from a first of the power supply terminals to said sleep transistor when in another mode than said power down mode.

76. The integrated circuit as claimed in claim 64 wherein said generator circuitry comprises a sleep generator.

77. The integrated circuit as claimed in claim 76 wherein said sleep generator comprises a charge pump circuit.

78. The integrated circuit as claimed in claim 64 wherein said sleep transistor has a similar threshold voltage as transistors in said cells.

79. The integrated circuit as claimed in claim 78 wherein said sleep transistor is a regular threshold voltage transistor.

80. A power management method comprising:

operating an integrated circuit having cells, each of the cells being a either a logic gate or a storage cell, said cells being in series with a sleep transistor electrically connected to a either a V_dd positive supply terminal or a V_ss ground terminal, the V_dd positive supply terminal and the V_ss ground terminal together defining a range of logic levels, and the operating of the integrated circuit including;

generating a variable voltage outside said range of logic levels; and

applying, in a power down mode, said variable voltage to the sleep transistor.

81. The power management method as claimed in claim 80 wherein the terminal is the V_ss terminal, said variable voltage outside the range of logic levels is a voltage lower than V_ss, and said sleep transistor is an n-channel transistor.

82. The power management method as claimed in claim 81 wherein said operating of the integrated circuit further includes applying V_dd to said sleep transistor when in another mode than said power down mode.

83. The power management method as claimed in claim 81 wherein said operating of the integrated circuit further includes applying a voltage greater than V_dd to said sleep transistor when in another mode than said power down mode.