METHODS AND APPARATUS RELATED TO LOSSLESS OPERATION WITHIN A DATA CENTER

• US 20100061367A1
• Filed: 06/30/2009
• Published: 03/11/2010
• Est. Priority Date: 09/11/2008
• Status: Abandoned Application

• Current Assignee: Juniper Networks Incorporated
• Original Assignee: Juniper Networks Incorporated
• Inventors: Aybay, Gunes, Frailong, Jean-Marc, Sindhu, Pradeep, Vohra, Quaizar, Venkatramani, Anjan
• Application Number:
  US12/495,344
• Publication Number:
  US 20100061367A1
• Time in Patent Office: Days
• US Class Current: 370/389
• CPC Class Codes: H04L 49/1515 Non-blocking multistage, e.g. Clos
• CPC Class Codes: H04L 49/351 for local area network [LAN], e.g. Ethernet switches
• CPC Class Codes: H04L 49/357 Fibre channel switches
• CPC Class Codes: H04L 49/602 Multilayer or multiprotocol switching, e.g. IP switching

Abstract

In one embodiment, an apparatus includes a switch core that defines a single logical entity and has a multi-stage switch fabric that has a set of stages physically distributed across a set of chassis. The set of stages collectively has a set of ingress ports and a set of egress ports. The switch core can be configured to be coupled to a set of peripheral processing devices via the set of ingress ports and the set of egress ports. The switch core can be configured to admit a set of cells associated with a packet into an ingress port from the set of ingress ports when delivery of the set of cells can be substantially guaranteed without loss through the multi-stage switch fabric.

Claims

1. An apparatus, comprising:

a switch core defining a single logical entity and having a multi-stage switch fabric having a plurality of stages physically distributed across a plurality of chassis, the plurality of stages collectively having a plurality of ingress ports and a plurality of egress ports, the switch core configured to be coupled to a plurality of peripheral processing devices via the plurality of ingress ports and the plurality of egress ports,

the switch core configured to admit a plurality of cells associated with a packet into an ingress port from the plurality of ingress ports when delivery of the plurality of cells can be substantially guaranteed without loss through the multi-stage switch fabric.

2. The apparatus of claim 1, wherein the plurality of peripheral processing devices includes a first peripheral processing device configured to communicate with a fiber channel protocol and a second peripheral processing device configured to communicate with a fiber-channel-over-Ethernet protocol.

3. The apparatus of claim 1, wherein the multi-stage switch fabric is configured as a deterministic network.

4. The apparatus of claim 1, wherein the multi-stage switch fabric is configured as a deterministic network such that the switch core admits the packet into an ingress port when the plurality of cells can be delivered to an egress port from the plurality of egress ports at a predetermined time.

5. The apparatus of claim 1, wherein:

the egress port is a first egress port,

the switch core is configured to send the plurality of cells associated with the packet from the ingress port to the first egress port and a second egress port from the plurality of egress ports.

6. The apparatus of claim 1, wherein:

the egress port is a first egress port,

the switch core is configured to send the plurality of cells associated with the packet from the ingress port to the first egress port and a second egress port from the plurality of egress ports without performing packet-loss processing at at least one stage from a plurality of stages of the multi-stage switch fabric.

7. The apparatus of claim 1, wherein:

the switch core includes a plurality of edge devices coupled to the multi-stage switch fabric via the plurality of ingress ports and the plurality of egress ports, the plurality of edge devices coupled to the plurality of peripheral processing devices, each edge device from the plurality of edge devices configured to receive the packet and define the plurality of cells based on the packet.

8. The apparatus of claim 1, wherein:

the switch core is configured to send the plurality of cells associated with the packet from the ingress port to an egress port from the plurality of egress ports via a plurality of stages of the multi-stage switch fabric without performing packet-loss processing at at least one stage from the plurality of stages.

9. An apparatus, comprising;

a switch core defining a single logical entity and having a switch fabric with a plurality of stages physically distributed across a plurality of chassis, the multi-stage switch fabric having a plurality of ingress ports and a plurality of egress ports, the switch core configured to be coupled to a plurality of peripheral processing devices via the plurality of ingress ports and the plurality of egress ports,

the switch core configured to receive a packet from an ingress port from the plurality of ingress ports, the switch core configured to send a plurality of cells associated with the packet from the ingress port to an egress port from the plurality of egress ports via the plurality of stages without performing packet-loss processing at at least one stage from the plurality of stages of the switch fabric.

10. The apparatus of claim 9, wherein the switch core is configured to be coupled to the plurality of peripheral processing devices including a first peripheral processing device configured to communicate with a fiber channel protocol and a second peripheral processing device configured to communicate with a fiber-channel-over-Ethernet protocol.

11. The apparatus of claim 9, wherein the multi-stage switch fabric is configured as a deterministic network such that the switch core admits a packet from an ingress port from the plurality of ingress ports only when delivery within the switch fabric of a plurality of cells associated with the packet can be substantially guaranteed without loss.

12. The apparatus of claim 9, wherein the multi-stage switch fabric is configured as a deterministic network such that the switch core admits a packet from an ingress port from the plurality of ingress ports when a plurality of cells associated with the packet can be delivered to an egress port from the plurality of egress ports at a predetermined time.

13. The apparatus of claim 9, wherein:

the egress port is a first egress port,

the switch core is configured to send the plurality of cells associated with the packet from the ingress port to the first egress port and a second egress port from the plurality of egress ports.

14. The apparatus of claim 9, wherein:

the egress port is a first egress port,

the switch core is configured to send the plurality of cells associated with the packet from the ingress port to the first egress port and a second egress port from the plurality of egress ports without performing packet-loss processing at at least one stage from the plurality of stages of the multi-stage switch fabric.

15. The apparatus of claim 9, wherein:

the switch core includes a plurality of edge devices coupled to the multi-stage switch fabric via the plurality of ingress ports and the plurality of egress ports, the plurality of edge devices coupled to the plurality of peripheral processing devices, each edge device from the plurality of edge devices configured to receive the packet and define the plurality of cells based on the packet.

16. The apparatus of claim 9, wherein:

the switch core is configured to send the plurality of cells associated with the packet from the ingress port to the egress port via the plurality of stages of the multi-stage switch fabric without performing packet-loss processing at at least one stage from the plurality of stages.

17. An apparatus, comprising;

a switch core defining a single logical entity and having a multi-stage switch fabric configured as a deterministic network, the multi-stage switch fabric having a plurality of ingress ports and a plurality of egress ports, the switch core configured to be coupled to a plurality of peripheral processing devices via the plurality of ingress ports and the plurality of egress ports,

the switch core configured to receive a packet from an ingress port from the plurality of ingress ports, the switch core configured to send a plurality of cells associated with the packet from the ingress port to an egress port from the plurality of egress ports.

18. The apparatus of claim 17, wherein the multi-stage switch fabric is physically distributed across a plurality of chassis.

19. The apparatus of claim 17, wherein the switch core is configured to be coupled to the plurality of peripheral processing devices including a first peripheral processing device configured to communicate with a fiber channel protocol and a second peripheral processing device configured to communicate with a fiber-channel-over-Ethernet protocol.

20. The apparatus of claim 17, wherein the multi-stage switch fabric is configured as the deterministic network such that the switch core admits a packet from an ingress port from the plurality of ingress ports only when delivery within the switch fabric of a plurality of cells associated with the packet can be substantially guaranteed without loss.

21. The apparatus of claim 17, wherein the multi-stage switch fabric is configured as the deterministic network such that the switch core admits a packet from an ingress port from the plurality of ingress ports when a plurality of cells associated with the packet can be delivered to an egress port from the plurality of egress ports at a predetermined time.

22. The apparatus of claim 17, wherein:

the egress port is a first egress port,

the switch core is configured to send the plurality of cells associated with the packet from the ingress port to the first egress port and a second egress port from the plurality of egress ports.

23. The apparatus of claim 17, wherein:

the egress port is a first egress port,

the multi-stage switch fabric having a plurality of stages physically distributed across a plurality of chassis,

the switch core is configured to send the plurality of cells associated with the packet from the ingress port to the first egress port and a second egress port from the plurality of egress ports without performing packet-loss processing at at least one stage from the plurality of stages of the multi-stage switch fabric.

24. The apparatus of claim 17, wherein:

the switch core includes a plurality of edge devices coupled to the multi-stage switch fabric via the plurality of ingress ports and the plurality of egress ports, the plurality of edge devices coupled to the plurality of peripheral processing devices, each edge device from the plurality of edge devices configured to receive the packet and define the plurality of cells based on the packet.

25. The apparatus of claim 17, wherein:

the switch core is configured to send the plurality of cells associated with the packet from the ingress port to the egress port via the plurality of stages of the multi-stage switch fabric without performing packet-loss processing at at least one stage from the plurality of stages.

26. The apparatus of claim 17, wherein:

the switch core is configured to send the plurality of cells associated with the packet from the ingress port to the egress port via a plurality of stages of the multi-stage switch fabric without performing packet-loss processing at at least one stage from the plurality of stages.