METHODS AND APPARATUS RELATED TO A LOW COST DATA CENTER ARCHITECTURE

• US 20100061391A1
• Filed: 09/11/2009
• Published: 03/11/2010
• Est. Priority Date: 09/11/2008
• Status: Active Grant

• Current Assignee: Juniper Networks Incorporated
• Original Assignee: Juniper Networks Incorporated
• Inventors: Aybay, Gunes, Frailong, Jean-Marc, Sindhu, Pradeep, Vohra, Quaizar, Venkatramani, Anjan
• Granted Patent: US 8,340,088 B2
• Time in Patent Office: Days
• US Class Current: 370/412
• CPC Class Codes: H04L 49/1515 Non-blocking multistage, e.g. Clos
• CPC Class Codes: H04L 49/3072 Packet splitting
• CPC Class Codes: H04L 49/35 Switches specially adapted for specific applications
• CPC Class Codes: H04L 49/356 for storage area networks
• CPC Class Codes: H04L 49/70 Virtual switches

Abstract

In one embodiment, an apparatus can include a first edge device that can have a packet processing module. The first edge device can be configured to receive a packet. The packet processing module of the first edge device can be configured to produce cells based on the packet. A second edge device can have a packet processing module configured to reassemble the packet based on the cells. A multi-stage switch fabric can be coupled to the first edge device and the second edge device. The multi-stage switch fabric can define a single logical entity. The multi-stage switch fabric can have switch modules. Each switch module from the switch modules can have a shared memory device. The multi-stage switch fabric can be configured to switch the cells so that the cells are sent to the second edge device.

Claims

1. An apparatus, comprising:

a first edge device having a packet processing module, the first edge device configured to receive a packet, the packet processing module of the first edge device configured to produce a plurality of cells based on the packet;

a second edge device having a packet processing module configured to reassemble the packet based on the plurality of cells; and

a multi-stage switch fabric coupled to the first edge device and the second edge device, the multi-stage switch fabric defining a single logical entity, the multi-stage switch fabric having a plurality of switch modules, each switch module from the plurality of switch modules having a shared memory device, the multi-stage switch fabric configured to switch the plurality of cells so that the plurality of cells are sent to the second edge device.

2. The apparatus of claim 1, wherein:

the multi-stage switch fabric having at least a first stage, a second stage and a third stage; and

the plurality of switch modules including a switch module associated with the first stage, a switch module associated with the second stage and a switch module associated with the third stage.

3. The apparatus of claim 1, wherein each switch module from the plurality of switch modules configured to switch a cell without performing Ethernet-based processing.

4. The apparatus of claim 1, wherein:

a switch module from the plurality of switch modules is configured to switch a cell from the plurality of cells based on a destination address of that cell and independent of an order in which that cell is received at that switch module relative to the remaining cells from the plurality of cells.

5. The apparatus of claim 1, wherein:

a switch module from the plurality of switch modules is configured to switch a cell from the plurality of cells based on a destination address of that cell, the destination address excluding a layer-2 address and a layer-4 address.

6. The apparatus of claim 1, wherein:

the multi-stage switch fabric has at least a first stage, a second stage and a third stage;

the plurality of switch modules includes a switch module associated with the first stage, a switch module associated with the second stage and a switch module associated with the third stage;

the switch module associated with the first stage is configured to store an address lookup table uniquely associated with the first stage and excluding a layer-2 Ethernet address and a layer-4 Ethernet address;

the switch module associated with the second stage is configured to store an address lookup table uniquely associated with the second stage and excluding a layer-2 Ethernet address and a layer-4 Ethernet address; and

the switch module associated with the third stage is configured to store an address lookup table uniquely associated with the third stage and excluding a layer-2 Ethernet address and a layer-4 Ethernet address.

7. The apparatus of claim 1, wherein:

the first edge device includes a memory device configured to define a queue having a length associated with a grant-request scheme; and

the shared memory device of each switch module from the plurality of switch modules configured to define a queue having a length associated with cell-switching synchronization, the length of the queue of each switch module from the plurality of switch modules being less the length of the queue of the first edge device.

8. The apparatus of claim 1, wherein:

the first edge device includes a buffer configured to define a queue having a length associated with a grant-request scheme; and

each switch module from the plurality of switch modules excluding a buffer configured to define a queue associated with the grant-request scheme.

9. An apparatus, comprising:

a multi-stage switch fabric defining a single logical entity, the multi-stage switch fabric configured to be coupled to a first edge device and a second edge device, the multi-stage switch fabric including a plurality of switch modules, each switch module from the plurality of switch modules including a shared memory device configured to define a queue having a length sufficient for the multi-stage switch fabric to implement cell-switching synchronization and insufficient for the multi-stage switch fabric to implement a congestion resolution scheme at that switch module.

10. The apparatus of claim 9, further comprising:

a plurality of ingress edge devices coupled to the multi-stage switch fabric, the plurality of ingress edge devices collectively having a plurality of input ports numbering more than 100,000 input ports, the plurality of ingress edge devices including the first edge device

a plurality of egress edge devices coupled to the multi-stage switch fabric, the plurality of egress edge devices collectively having a plurality of output ports numbering more than 100,000 input ports, the plurality of egress edge devices including the second edge device; and

the multi-stage switch fabric having a plurality of input ports and configured to receive a plurality of cells distributed non-uniformly across the plurality of input ports of the multi-stage switch fabric over a period of time.

11. The apparatus of claim 9, wherein:

the multi-stage switch fabric has at least a first stage, a second stage and a third stage;

the plurality of switch modules includes a switch module associated with the first stage, a switch module associated with the second stage and a switch module associated with the third stage;

the switch module associated with the first stage is configured to store an address lookup table associated with the first stage and excluding a layer-2 address and a layer-4 address;

the switch module associated with the second stage is configured to store an address lookup table associated with the second stage and excluding a layer-2 address and a layer-4 address; and

the switch module associated with the third stage is configured to store as address lookup table uniquely associated with the third stage and excluding a layer-2 address and a layer-4 address.

12. The apparatus of claim 9, wherein:

the multi-stage switch fabric configured to receive a plurality of cells from the first edge device, the plurality of cells being associated with at least one packet at the first edge device,

the multi-stage switch fabric being reconfigurable and having a reconfiguration period associated with a time length of a cell from the plurality of cells,

each switch module from the plurality of switch modules is configured to switch a cell without performing Ethernet-based processing.

13. A method, comprising:

receiving a plurality of cells at a plurality of input ports of a multi-stage switch fabric, each cell from the plurality of cells being associated with a packet from a plurality of packets received by a plurality of ingress edge devices; and

switching each cell from the plurality of cells through a multi-stage switch fabric without performing Ethernet-based processing within the multi-stage switch fabric, the multi-stage switch fabric defining a single Ethernet hop between the plurality of ingress edge devices and a plurality of egress edge devices, the multi-stage switch fabric having a plurality of switch modules, each switch module from the plurality of switch modules having a shared memory device.

14. The method of claim 13, wherein:

the plurality of ingress edge devices collectively includes a plurality of input ports numbering more than 100,000 input ports; and

the plurality of cells being distributed non-uniformly across the plurality of input ports of the multi-stage switch fabric over a period of time.

15. The method of claim 13, wherein:

the switching is performed based on a destination address of that cell, the destination address excluding a layer-2 Ethernet address and a layer-4 Ethernet address.

16. The method of claim 13, further comprising:

processing the plurality of packets at the plurality of ingress edge devices to define the plurality of cells, the switching being performed without Ethernet-based processing within the multi-stage switch fabric; and

reassembling the plurality of packets at the plurality of egress edge devices based on the plurality of cells.

17. The method of claim 13, further comprising:

processing the plurality of packets at the plurality of ingress edge devices to define the plurality of cells; and

reassembling the plurality of packets at the plurality of egress edge devices based on the plurality of cells, the reassembling including reordering the plurality of cells such that the plurality of packets are reassembled, the switching being performed without determining an order the plurality of cells within the multi-stage switch fabric.

18. The method of claim 13, wherein:

the switching includes buffering the plurality of cells within the shared memory devices of the plurality of switch modules to correct for cell-switching synchronization without resolving congestion within the multi-stage switch fabric according to a grant-request scheme.

19. The method of claim 13, wherein:

the switching is performed without queuing within the multi-stage switch fabric based on congestion at the plurality of ingress edge devices or the plurality of egress edge devices.

20. The method of claim 13, wherein:

the switching is performed at each stage of the multi-stage switch fabric; and

the switching is performed without performing Ethernet-based processing at each stage of the multi-stage switch fabric.