THIN-FILM TRANSISTOR, METHOD OF MANUFACTURING THE SAME, LIQUID CRYSTAL DISPLAY PANEL HAVING THE SAME AND ELECTRO-LUMINESCENCE DISPLAY PANEL HAVING THE SAME

• US 20100062574A1
• Filed: 10/22/2009
• Published: 03/11/2010
• Est. Priority Date: 10/28/2005
• Status: Active Grant

• Current Assignee: Samsung Display Company Limited (Samsung Electronics Co. Ltd.)
• Original Assignee: Samsung Electronics Co. Ltd.
• Inventors: Choi, Yong-Mo, KIM, Byoung-June, Oh, Min-Seok, Choi, Jae-Ho, Yang, Sung-Hoon
• Granted Patent: US 8,088,653 B2
• Time in Patent Office: Days
• US Class Current: 438/158
• CPC Class Codes: H01L 27/12 the substrate being other than a semiconductor body, e.g. an insulating body
• CPC Class Codes: H01L 27/124 with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits wiring structures per se H01L23/52
• CPC Class Codes: H01L 29/458 for thin film silicon, e.g. source or drain electrode
• CPC Class Codes: H01L 29/66765 Lateral single gate single channel transistors with inverted structure, i.e. the channel layer is formed after the gate
• CPC Class Codes: H01L 29/78669 with inverted-type structure, e.g. with bottom gate

Abstract

A TFT includes a gate electrode, an active layer, a source electrode, a drain electrode, and a buffer layer. The gate electrode is formed on the substrate; the active layer is formed on the gate electrode. The source and drain electrodes, formed on the active layer, are separated by a predetermined distance. The buffer layer is formed between the active layer and the source and drain electrodes. The buffer layer has a substantially continuously varying content ratio corresponding to a buffer layer thickness. The buffer layer is formed to suppress oxidation of the active layer, and reduce contact resistance.

Claims

1-12. -12. (canceled)

13. A method of manufacturing a thin-film transistor comprising:

forming a gate electrode on a base substrate;

forming a gate insulation layer on the substrate to cover the gate electrode;

forming an active layer on the gate insulation layer to cover the gate electrode;

forming a buffer layer on the active layer to suppress an oxidation of the active layer;

primarily etching first predefined portions of the buffer layer and the active layer;

forming a source electrode and a drain electrode on the primarily etched active layer, wherein the source electrode and the drain electrode are separated from each other by a predetermined distance; and

secondarily etching second predefined portions of the buffer layer and the active layer, using as an etching mask at least one of the source electrode and the drain electrode.

14. The method of claim 13, wherein the buffer layer comprises a plurality of films formed by an in-situ process on the active layer.

15. The method of claim 14, wherein the buffer layer comprises a first connection layer, a second connection layer, and a third connection layer.

16. The method of claim 15, wherein the active layer comprises silicon.

17. The method of claim 16, wherein the first connection layer comprises titanium silicide, wherein the second connection layer comprises titanium, and wherein the third connection layer comprises titanium nitride.

18. The method of claim 17, wherein the first connection layer is formed by introducing hydrogen gas, silane gas, and titanium chloride gas into a chamber, wherein the second connection layer is formed by introducing hydrogen gas and titanium chloride gas into the chamber, and wherein the third connection layer is formed by introducing hydrogen gas, titanium chloride gas, and ammonia gas into the chamber.

19. The method of claim 18, wherein a flow rate of the silane gas is gradually decreased and a flow rate of the titanium chloride gas is gradually increased when forming the first connection layer, and wherein a flow rate of the titanium chloride gas is gradually decreased and a flow rate of the ammonia gas is gradually increased when forming the third connection layer.

20. The method of claim 16, wherein the first connection layer comprises molybdenum silicide, wherein the second connection layer comprises molybdenum, and wherein the third connection layer comprises molybdenum nitride.

21. The method of claim 20, wherein the first connection layer is formed by introducing hydrogen gas, silane gas, and molybdenum chloride gas into a chamber, wherein the second connection layer is formed by introducing hydrogen gas and molybdenum chloride gas into the chamber, and wherein the third connection layer is formed by introducing hydrogen gas, molybdenum chloride gas, and ammonia gas into the chamber.

22. The method of claim 21, wherein a flow rate of the silane gas is gradually decreased and a flow rate of the molybdenum chloride gas is gradually increased when forming the first connection layer, and wherein a flow rate of the molybdenum chloride gas is gradually decreased and a flow rate of the ammonia gas is gradually increased when forming the third connection layer.

23. The method of claim 13, further comprising:

primarily etching the first predefined portions of the buffer layer; and

using the primarily etched buffer layer as an etching mask, primarily etching the first predefined portions of the active layer.

24. The method of claim 13, wherein etching the first predefined portions of the buffer layer is performed using a chlorine-containing gas.

25. The method of claim 13, wherein etching the first predefined portions of the active layer is performed using a fluorine-containing gas.

26. The method of claim 25, wherein the active layer comprises a semiconductor layer and an impurity layer, and wherein secondarily etching the second predefined portions of the active layer is performed on predefined portions of the impurity layer.

27-32. -32. (canceled)