SELF-ALIGNED TRENCH FORMATION

• US 20100062579A1
• Filed: 09/11/2008
• Published: 03/11/2010
• Est. Priority Date: 09/11/2008
• Status: Active Grant

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micron Technology, Inc.
• Inventors: Lane, Richard, Juengling, Werner
• Granted Patent: US 8,101,497 B2
• Time in Patent Office: Days
• US Class Current: 438/424
• CPC Class Codes: H01L 21/3086 characterised by the process involved to create the mask, e.g. lift-off masks, sidewalls, or to modify the mask, e.g. pre-treatment, post-treatment
• CPC Class Codes: H01L 21/3088 Process specially adapted to improve the resolution of the mask
• CPC Class Codes: H01L 21/31053 involving a dielectric removal step
• CPC Class Codes: H01L 21/76224 using trench refilling with dielectric materials trench filling with polycristalline silicon H01L21/763; together with vertical isolation, e.g. trench refilling in a SOI substrate H01L21/76264
• CPC Class Codes: H01L 29/0649 Dielectric regions, e.g. SiO2 regions, air gaps
• CPC Class Codes: H10B 12/0387 Making the trench

Abstract

Methods for forming a semiconductor device include forming self-aligned trenches, in which a first set of trenches is used to align a second set trenches. Methods taught herein can be used as a pitch doubling technique, and may therefore enhance device integration. Further, employing a very thin CMP stop layer, and recessing surrounding materials by about an equal amount to the thickness of the CMP stop layer, provides improved planarity at the surface of the device.

Claims

1. A method of forming a device, the method comprising:

forming a layer of polysilicon on a substrate;

forming a first set of trenches in the substrate, wherein remaining portions of the polysilicon layer remain above the substrate in inter-trench regions between trenches of the first set;

filling the first set of trenches with a filler material, wherein the filler material extends upward to at least a level adjacent the remaining portions of the polysilicon layer;

selectively etching the remaining portions of the polysilicon layer from the inter-trench regions;

forming spacers on sidewalls of the filler material in the inter-trench regions; and

etching a second set of trenches into the substrate between the spacers.

2. The method of claim 1, further comprising, after filling, planarizing the filler material on the substrate to expose the remaining portions of the polysilicon layer in the inter-trench region prior to selectively etching the remaining portions of the polysilicon layer.

3. The method of claim 1, wherein forming a layer of polysilicon comprises forming a layer of polysilicon with a thickness between about 500 Å

and 3000 Å

.

4. The method of claim 1, wherein etching the second set of trenches comprises etching a second set of trenches that is substantially parallel to the first set of trenches.

5. The method of claim 4, wherein etching the second set of trenches comprises separating trenches of the first set of trenches from trenches of the second set of trenches by a width less than F, wherein F is a minimum feature size formable using a photolithographic technique.

6. The method of claim 5, wherein after etching the second set of trenches, the trenches of the first and second sets of trenches are approximately uniformly spaced and have approximately uniform widths.

7. The method of claim 5, wherein the trenches of the first set have a depth greater than a depth of the second set.

8. The method of claim 1, wherein forming a first set of trenches comprises etching the first set of trenches through a hard mask layer over the layer of polysilicon.

9. The method of claim 8, wherein the hard mask layer comprises tetraethylorthosilicate (“

TEOS”

).

10. The method of claim 8, further comprising, before etching the first set of trenches, forming spacers on at least a portion of sidewalls of the hard mask layer.

11. The method of claim 8, wherein the first set of trenches has a depth from a top surface of the inter-trench regions to the bottom of the first set of trenches of between about 2000 Å

and 2500 Å

immediately after the step of forming the first set of trenches.

12. The method of claim 8, wherein the first set of trenches has an aspect ratio of between about 5:

1 and 100;

1, wherein the aspect ratio is the ratio between a depth of the first set of trench and a width of trenches of the first set, wherein depth is calculated from the top surface of the inter-trench regions to the bottom of the first set of trenches.

13. The method of claim 8, further comprising using a carbon hard mask to pattern the hard mask layer and removing the carbon hard mask before etching the first set of trenches.

14. The method of claim 13, wherein the carbon hard mask has a thickness between about 1800 Å

and 2200 Å

.

15. The method of claim 14, wherein the hard mask layer has a thickness between about 500 Å

and 1500 Å

.

16. The method of claim 1, further comprising forming an etch stop layer beneath the layer of polysilicon and, after etching the second set of trenches, filling the second set of trenches with a second filler material and planarizing the second filler material, wherein planarizing the second filler material comprises stopping on the etch stop layer.

17. A method of forming a device on a substrate, comprising:

forming an etch stop layer on the substrate;

etching a plurality of first trenches through the etch stop layer and the substrate;

filling the first trenches with an isolation material that protrudes above the substrate;

forming spacers on sidewalls of the protruding portion of the isolation material;

etching a plurality of second trenches between the spacers;

filling the second trenches with a second filler material; and

planarizing the second filler material and stopping planarizing on the etch stop layer.

18. The method of claim 17, wherein forming an etch stop comprises forming the etch stop with a thickness between about 20 Å

and 150 Å

.

19. The method of claim 17, wherein planarizing comprises chemical mechanical planarization.

20. The method of claim 17, wherein forming an etch stop comprises forming the etch stop of silicon nitride.

21. The method of claim 17, wherein forming an etch stop comprises forming the etch stop of aluminum oxide.

22. The method of claim 17, wherein filling the first trenches with an isolation material that protrudes above the substrate comprises:

overfilling the trenches with an isolation material;

planarizing the isolation material to expose placeholder material underlying the isolation material between sidewalls of the first trenches;

selectively etching the placeholder material between sidewalls of the first trenches.

23. The method of claim 22, wherein overfilling the trenches with an isolation material comprises overfilling the trenches with a spin-on dielectric.

24. The method of claim 22, wherein filling each of the first trenches further comprises lining the trenches with at least one liner layer.

25. The method of claim 17, wherein etching a plurality of second trenches comprises spacing the second trenches apart from the first trenches by a width less than F, wherein F is a minimum feature size formable using a photolithographic technique.

26. The method of claim 17, wherein etching a plurality of second trenches comprises etching the second trenches to a depth less than a depth of the first trenches.

27. A method of forming an integrated circuit, comprising:

forming a structure on a substrate, the structure comprising a structural material and an etch stop, the etch stop having an upper surface and a lower surface;

planarizing the structure and stopping planarizing on the etch stop;

selectively recessing the structural material to be approximately coplanar with the lower surface of the etch stop; and

selectively removing the etch stop.

28. The method of claim 27, wherein the structural material comprises a form of silicon oxide.

29. The method of claim 27, wherein the etch stop comprises nitride.

30. The method of claim 29, wherein the etch stop comprises Si₃N₄.

31. The method of claim 27, wherein, before selectively removing the etch stop and after planarizing, the etch stop has a thickness between about 10 Å

and 70 Å

.

32. The method of claim 27, wherein selectively recessing the structural material to approximately coplanar with the lower surface of the etch stop comprises selectively recessing the structural material to a level within ±

20 Å

of the lower surface of the etch stop.