METHOD FOR FORMING GATE SPACERS FOR SEMICONDUCTOR DEVICES

• US 20100062592A1
• Filed: 09/09/2008
• Published: 03/11/2010
• Est. Priority Date: 09/09/2008
• Status: Abandoned Application

• Current Assignee: Tokyo Electron Limited
• Original Assignee: Tokyo Electron Limited
• Inventors: Clark, Robert D.
• Application Number:
  US12/206,949
• Publication Number:
  US 20100062592A1
• Time in Patent Office: Days
• US Class Current: 438/591
• CPC Class Codes: H01L 21/28176 with a treatment, e.g. annealing, after the formation of the definitive gate conductor
• CPC Class Codes: H01L 21/67184 characterized by the presence of more than one transfer chamber
• CPC Class Codes: H01L 21/67207 comprising a chamber adapted to a particular process
• CPC Class Codes: H01L 29/51 Insulating materials associated therewith for MIS structures on thin film semiconductor H01L29/4908
• CPC Class Codes: H01L 29/6656 using multiple spacer layers, e.g. multiple sidewall spacers

Abstract

A method for forming gate spacers for semiconductor devices includes forming a patterned gate structure on substrate, where the patterned gate structure contains an interface layer on the substrate, a high-k film on the interface layer, and a gate electrode on the high-k film. The method further includes depositing a nitride barrier layer on the patterned gate structure using processing conditions that minimize or prevent oxidation of the substrate and the gate electrode, depositing a spacer material on the nitride barrier layer, and anisotropically etching the spacer material to form a gate spacer on the patterned gate structure.

Claims

1. A method for forming a semiconductor device, the method comprising:

forming a patterned gate structure on a substrate, the patterned gate structure comprising an interface layer on the substrate, a high-k film on the interface layer, and a gate electrode on the high-k film;

depositing a nitride barrier layer on the patterned gate structure in a process chamber, the depositing comprising;

exposing the patterned gate structure to a process gas containing a nitride precursor at a substrate temperature below 400°

C., and

maintaining a partial pressure of oxygen-containing gases below 1×

10<sup>−

4</sup> Torr in the process chamber during the exposing;

depositing a spacer material on the nitride barrier layer; and

anisotropically etching the spacer material to form a gate spacer on the patterned gate structure.

2. The method of claim 1, wherein the gate electrode comprises poly Si.

3. The method of claim 1, wherein the gate electrode comprises a metal-containing layer.

4. The method of claim 3, wherein the metal-containing layer directly contacts the high-k film.

5. The method of claim 3, wherein the gate electrode comprises W, WN, WSi, Al, Mo, Ta, TaN, TaSiN, TaAlN, HfN, HfSiN, Ti, TiN, TiSiN, Mo, MoN, Re, Pt, or Ru, or a combination of two or more thereof.

6. The method of claim 1, wherein the high-k film comprises a metal oxide or a metal oxynitride.

7. The method of claim 6, wherein the high-k film comprises HfO₂, HfON, ZrO₂, ZrON, TiO₂, TiON, Al₂O₃, La₂O₃, W₂O₃, CeO₂, Y₂O₃, or Ta₂ O₅, or a combination of two or more thereof.

8. The method of claim 1, wherein the nitride barrier layer comprises SiN, SiCN, or a combination thereof.

9. The method of claim 1, wherein the spacer material comprises SiN, SiCN, or SiO₂, or a combination thereof.

10. The method of claim 1, wherein a thickness of the nitride barrier layer on sidewalls of the gate electrode is between about 10 angstrom and about 50 angstrom.

11. The method of claim 1, wherein, on sidewalls of the gate electrode, a thickness of the spacer material is greater than a thickness of the nitride barrier layer.

12. The method of claim 1, wherein the nitride barrier layer and the spacer material are selected from SiN and SiCN.

13. The method of claim 1, wherein the nitride barrier layer comprises SiN or SiCN and the spacer material comprises SiO₂.

14. The method of claim 1, wherein the nitride barrier layer is deposited by ALD or PEALD and the spacer material is deposited by CVD or PECVD.

15. A method for forming a semiconductor device, the method comprising:

forming a patterned gate structure on a substrate, the patterned gate structure comprising an interface layer on the substrate, a high-k film on the interface layer, a metal-containing gate electrode directly contacting the high-k film;

depositing a nitride barrier layer containing SiN or SiCN on the patterned gate structure in a process chamber, the depositing comprising;

exposing the patterned gate structure to a process gas containing a SiN or SiCN precursor at a substrate temperature below 400°

C., and

maintaining a partial pressure of oxygen-containing gases below 1×

10<sup>−

4</sup> Torr in the process chamber during the exposing;

depositing a SiO₂ spacer material on the nitride barrier layer; and

anisotropically etching the SiO₂ spacer material to form a gate spacer on the patterned gate structure.

16. The method of claim 15, wherein a thickness of the nitride barrier layer on sidewalls of the metal-containing gate electrode is between about 10 angstrom and about 50 angstrom.

17. The method of claim 15, wherein the nitride barrier material is deposited by ALD or PEALD and the SiO₂ spacer material is deposited by CVD or PECVD.

18. A method for forming a semiconductor device, the method comprising:

forming a patterned gate structure on a substrate, the patterned gate structure comprising an interface layer on the substrate, a high-k film on the interface layer, and a metal-containing gate electrode directly contacting the high-k film;

depositing a nitride barrier layer containing SiN or SiCN by ALD or PEALD on the patterned gate structure in a process chamber, wherein a thickness of the nitride barrier layer on sidewalls of the patterned gate structure is between about 10 angstrom and about 50 angstrom, the depositing comprising;

exposing the patterned gate structure to a process gas containing a SiN or SiCN precursor at a substrate temperature below 400°

C., and

maintaining a partial pressure of oxygen-containing gases below 1×

10<sup>−

4</sup> Torr in the process chamber during the exposing;

depositing a SiN or SiCN spacer material on the nitride barrier layer; and

anisotropically etching the spacer material to form a gate spacer on the patterned gate structure.

19. The method of claim 18, wherein the spacer material is deposited by CVD or PECVD.

20. The method of claim 18, wherein, on the sidewalls of the metal-containing gate electrode, a thickness of the spacer material is greater than a thickness of the nitride barrier layer.