SEMICONDUCTOR DEVICES SUITABLE FOR NARROW PITCH APPLICATIONS AND METHODS OF FABRICATION THEREOF

• US 20100062603A1
• Filed: 09/11/2009
• Published: 03/11/2010
• Est. Priority Date: 09/11/2008
• Status: Active Grant

• Current Assignee: Applied Materials Incorporated
• Original Assignee: Applied Materials Incorporated
• Inventors: Nguyen, Vicky U., Yokota, Yoshita, Poon, Tze Wing, Swenberg, Johanes, Srinivasan, Swaminathan, Sun, Shiyu, Liu, Wei, Ganguly, Udayan, Tang, Jing, Newman, Jacob, Olsen, Christopher Sean, Thirupapuliyur, Sunderraj
• Granted Patent: US 8,871,645 B2
• Time in Patent Office: Days
• US Class Current: 438/694
• CPC Class Codes: H01L 21/67167 surrounding a central transfer chamber
• CPC Class Codes: H01L 21/67207 comprising a chamber adapted to a particular process
• CPC Class Codes: H01L 21/76232 of trenches having a shape other than rectangular or V-shape, e.g. rounded corners, oblique or rounded trench walls H01L21/76229 takes precedence
• CPC Class Codes: H01L 29/788 with floating gate H01L29/78391 takes precedence
• CPC Class Codes: H10B 41/30 characterised by the memory core region

Abstract

Semiconductor devices suitable for narrow pitch applications and methods of fabrication thereof are described herein. In some embodiments, a semiconductor device may include a floating gate having a first width proximate a base of the floating gate that is greater than a second width proximate a top of the floating gate. In some embodiments, a method of shaping a material layer may include (a) oxidizing a surface of a material layer to form an oxide layer at an initial rate; (b) terminating formation of the oxide layer when the oxidation rate is about 90% or below of the initial rate; (c) removing at least some of the oxide layer by an etching process; and (d) repeating (a) through (c) until the material layer is formed to a desired shape. In some embodiments, the material layer may be a floating gate of a semiconductor device.

Claims

1. A method of shaping a material layer, comprising:

(a) oxidizing a surface of a material layer to form an oxide layer at an initial rate;

(b) terminating formation of the oxide layer when the oxidation rate is about 90% or below of the initial rate;

(c) removing at least some of the oxide layer by an etching process; and

(d) repeating (a) through (c) until the material layer is formed to a desired shape.

2. The method of claim 1, wherein terminating formation of the oxide layer further comprises:

terminating formation of the oxide layer when the oxidation rate is between about 0% to about 90% of the initial rate.

3. The method of claim 1, wherein the material layer comprises polysilicon, silicon, or a metal.

4. The method of claim 1, wherein oxidizing the material layer to form the oxide layer is performed by at least one of wet or dry rapid thermal oxidation, radical oxidation, plasma oxidation, wet or dry chemical oxidation, or photochemical oxidation, and wherein the etch process comprises at least one of wet or dry chemical etch, reactive ion etch, or plasma etch.

6. The method of claim 1, further comprising:

providing a substrate having a tunnel oxide layer, the material layer disposed above the tunnel oxide layer, and a shallow trench isolation region disposed adjacent to the tunnel oxide layer.

7. The method of claim 6, wherein the material layer is a floating gate formed into the desired shape having a first width proximate a base of the floating gate that is greater than a second width proximate a top of the floating gate.

8. The method of claim 7, wherein a width of the floating gate decreases non-linearly from the first width to the second width.

9. The method of claim 7, wherein the tunnel oxide layer thickens between about 0 to about 2 nanometers during (a) through (d).

10. The method of claim 6, wherein the shallow trench isolation region is further disposed adjacent to the material layer.

11. The method of claim 10, wherein the material layer is a floating gate formed into the desired shape having a first width proximate a base of the floating gate that is substantially equivalent to a second width proximate a top of the floating gate.

12. The method of claim 11, wherein a height of the floating gate is between about 1 to about 10 nanometers.

13. The method of claim 11, wherein the top of the floating gate and a top of the shallow trench isolation region are substantially planar.

14. The method of claim 13, further comprising:

depositing an inter-poly dielectric layer atop the floating gate and the shallow trench isolation region; and

depositing a conductive layer atop the inter-poly dielectric layer.

15. The method of claim 1, further comprising:

providing a substrate having the material layer disposed thereon and having a mask layer disposed atop an upper surface of the material layer.

16. The method of claim 15, wherein the mask layer comprises at least one of an oxide layer, a nitride layer, a silicide layer, or a silicate layer.

17. The method of claim 15, wherein the material layer is formed into the desired shape having a first width proximate a base of the desired shape that is substantially equivalent to a second width proximate a top of the desired shape.

18. The method of claim 17, wherein the desired shape has an aspect ratio of between about 0.5 to about 20 nanometers.

19. The method of claim 17, wherein the first and second width of the desired shape is between about 1 to about 30 nanometers.

20. The method of claim 17, wherein a height of the desired shape is between about 1 to about 30 nanometers.

21. The method of claim 17, further comprising at least one of oxidizing or removing an exposed portion of the substrate during (a) through (d).

22. The method of claim 21, wherein the substrate further comprises a raised portion having the material layer disposed thereon after (a) through (d).

23. The method of claim 22, wherein the raised portion has a width proximate the first and second width of the desired shape of the material layer.

24. The method of claim 17, wherein the substrate comprises at least one of a silicon-containing layer, an oxygen-containing layer, or a non-silicon containing layer.

25. The method of claim 24, wherein the material layer comprises silicon.

26. The method of claim 1, wherein removing at least some of the oxide layer by an etching process further comprises:

terminating the etch process when the etch rate is about 90% or below of an initial etch rate.

5. (canceled)

27-57. -57. (canceled)