INFORMATION PROCESSING DEVICE INCLUDING MEMORY MANAGEMENT DEVICE MANAGING ACCESS FROM PROCESSOR TO MEMORY AND MEMORY MANAGEMENT METHOD

• US 20100064111A1
• Filed: 09/09/2009
• Published: 03/11/2010
• Est. Priority Date: 09/09/2008
• Status: Active Grant

• Current Assignee: Kioxia Corporation
• Original Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Inventors: Kunimatsu, Atsushi, Miyagawa, Masaki, Nakai, Hiroto, Maeda, Kenichi, Kawagome, Kazuhiro, Nozue, Hiroshi, Sakamoto, Hiroyuki
• Granted Patent: US 9,280,466 B2
• Time in Patent Office: Days
• US Class Current: 711/161
• CPC Class Codes: G06F 12/0246 in block erasable memory, e.g. flash memory
• CPC Class Codes: G06F 12/08 in hierarchically structured memory systems, e.g. virtual memory systems
• CPC Class Codes: G06F 12/0804 with main memory updating G06F12/0806 takes precedence
• CPC Class Codes: G06F 12/0888 using selective caching, e.g. bypass
• CPC Class Codes: G06F 2212/1036 Life time enhancement
• CPC Class Codes: G06F 2212/2022 Flash memory
• CPC Class Codes: G06F 2212/205 Hybrid memory, e.g. using both volatile and non-volatile memory
• CPC Class Codes: G06F 2212/7201 Logical to physical mapping or translation of blocks or pages

Abstract

A device according to an example of the invention comprises a section which accepts a write destination logical address and write target data from a processor, the write destination logical address indicating a write position to write the write target data into a composite memory which includes a first memory and a nonvolatile second memory, a section which determines a write destination physical address corresponding to the write destination logical address so that the number of times of access to the second memory is smaller than the number of times of access to the first memory, a section which stores, in a storage section, address conversion data associating the write destination logical address with the write destination physical address, and a section which writes the write target data into a position in the composite memory indicated by the write destination physical address.

Claims

1. An information processing device including a memory management device, comprising:

an accepting section which accepts a write destination logical address and write target data from a processor, the write destination logical address indicating a write position to write the write target data into a composite memory which includes a first memory and a nonvolatile second memory;

an address determining section which determines a write destination physical address corresponding to the write destination logical address so that the number of times of access to the second memory is smaller than the number of times of access to the first memory;

an address management section which stores, in a storage section, address conversion data associating the write destination logical address with the write destination physical address; and

a writing section which writes the write target data into a position in the composite memory indicated by the write destination physical address.

2. The information processing device according to claim 1, wherein

the address determining section determines the write destination physical address of the write target data for the composite memory on the basis of at least one of an importance and access frequency of the write target data, and

at least one of the importance and access frequency of the write target data is determined on the basis of at least one of a type of the write target data, data set by an user, and access frequency information for the write target data.

3. The information processing device according to claim 1, wherein

the address determining section determines whether the write target data belongs to a group having a high access frequency or a group having a low access frequency on the basis of at least one of an importance and access frequency of the write target data, when determining that the write target data belongs to the group having the high access frequency, the address determining section determines an unused physical address in the first memory as the write destination physical address, and when determining that the write target data belongs to the group having the low access frequency, the address determining section determines an unused physical address in the second memory as the write destination physical address.

4. The information processing device according to claim 2, wherein

the importance is obtained on the basis of at least one of the type of the write target data, user set data which associates a characteristic of the write target data with the importance, and an unused time from a last access to the write target data to a present time.

5. The information processing device according to claim 2, wherein

the access frequency is obtained on the basis of at least one of an estimated value of the access frequency determined by the type of the write target data and an observed value of the access frequency of the write target data.

6. The information processing device according to claim 1, wherein

the storage section stores data peculiarity information including access frequency information peculiar to the write target data, and

the address determining section determines the write destination physical address of the write target data for the composite memory on the basis of the data peculiarity information so that the access frequency in the first memory is higher than the access frequency in the second memory and so that the access frequency is equal in each of the first and second memories.

7. The information processing device according to claim 1, wherein

the storage section stores memory usage information including the number of times of each access to area in the composite memory, and

the address determining section determines the write destination physical address of the write target data for the composite memory on the basis of the memory usage information so that the access frequency in the first memory is higher than the access frequency in the second memory and so that the access frequency is equal in each of the first and second memories.

8. The information processing device according to claim 1, wherein

the storage section stores a page size and a block size of the composite memory and memory peculiarity information including the number of times of permitted access to each area of the composite memory, and

the address determining section determines the write destination physical address of the write target data for the composite memory on the basis of the memory peculiarity information so that the access frequency in the first memory is higher than the access frequency in the second memory and so that the access frequency is equal in each of the first and second memories.

9. The information processing device according to claim 1, wherein

the address determining section changes a threshold value which is used to determine whether to store the write target data in the first memory or the second memory in accordance with information on the usage rate of the first memory or information on the usage rate of the second memory.

10. The information processing device according to claim 1, wherein

the write target data includes a data main part and access frequency information corresponding to the data main part, and

the address determining section determines the write destination physical address on the basis of the access frequency information included in the write target data.

11. The information processing device according to claim 1, wherein

the access frequency information for the write target data is managed by an operating system or settable by an user.

12. The information processing device according to claim 1, wherein

the first memory is a volatile semiconductor memory, and the second memory includes a first nonvolatile semiconductor memory block which is possible to store M (an integral number equal to or more than 1) bits in one memory cell and a second nonvolatile semiconductor memory block which is possible to store M+1 or more bits in one memory cell;

and the address determining section determines whether the write target data belongs to a high access frequency group, a medium access frequency group or a low access frequency group on the basis of at least one of an importance and access frequency of the write target data, the address determining section determining an unused physical address in the nonvolatile semiconductor memory as the write destination physical address when determining that the write target data belongs to the high access frequency group, the address determining section determining an unused physical address in the first nonvolatile semiconductor memory block as the write destination physical address when determining that the write target data belongs to the medium access frequency group, the address determining section determining an unused physical address in the second nonvolatile semiconductor memory block as the write destination physical address when determining that the write target data belongs to the low access frequency group.

13. The information processing device according to claim 1, further comprising:

a relocating section which determines, in accordance with a dynamic change of at least one of an importance and access frequency of the write target data from that in previous writing, a relocated write destination physical address and relocates the write target data stored in one of the first memory and the second memory to another memory, the relocated write destination physical address being used in the relocation of the write target data to the other memory,

wherein the address management section updates the address conversion data stored in the storage section in accordance with the relocated write destination physical address.

14. The information processing device according to claim 12, further including:

a relocating section which determines, in accordance with a dynamic change of at least one of the importance and access frequency of the write target data from that in previous writing, a relocated write destination physical address and relocates the write target data stored in one of the first nonvolatile semiconductor memory block and the second nonvolatile semiconductor memory block to another memory block, the relocated write destination physical address being used in the relocation of the write target data to the other memory block,

wherein the address management section updates the address conversion data stored in the storage section in accordance with the relocated write destination physical address.

15. The information processing device according to claim 1, wherein

the accepting section accepts a read destination logical address from the processor,

the information processing device further comprising:

an address conversion section which converts the read destination logical address into a read destination physical address for the composite memory on the basis of the address conversion data stored in the storage section;

a reading section which reads read target data corresponding to the read destination physical address from the composite memory; and

a transfer section which transfers the read target data to the processor.

16. The information processing device according to claim 15, wherein

the transfer section stores, in a work storage section, data read from the composite memory, and sends, to the processor, the read target data corresponding to the read destination physical address included in the data stored in the work storage section.

17. The information processing device according to claim 15, wherein

an unit of writing and reading in the composite memory is equal to a page size, a multiple of the page size, a block size or a multiple of the block size.

18. A memory management method comprising:

accepting a write destination logical address and write target data from a processor, the write destination logical address indicating a write position to write the write target data into a composite memory which includes a first memory and a nonvolatile second memory;

determining a write destination physical address corresponding to the write destination logical address so that the number of times of access to the second memory is smaller than the number of times of access to the first memory;

storing, in a storage section, address conversion data associating the write destination logical address with the write destination physical address; and

writing the write target data into a position in the composite memory indicated by the write destination physical address.

19. The memory management method according to claim 18, further comprising:

determining, in accordance with a dynamic change of at least one of an importance and access frequency of the write target data from that in previous writing, a relocated write destination physical address after the writing and relocates the write target data stored in one of the first memory and the second memory to another memory, the relocated write destination physical address being used in the relocation of the write target data to the other memory; and

updating the address conversion data stored in the storage section in accordance with the relocated write destination physical address.

20. The memory management method according to claim 18, further comprising:

accepting a read destination logical address from the processor;

converting the read destination logical address into a read destination physical address for the composite memory on the basis of the address conversion data stored in the storage section;

reading read target data corresponding to the read destination physical address from the composite memory; and

transferring the read target data to the processor.