RESISTIVE MEMORY DEVICE AND METHOD OF FABRICATING THE SAME

• US 20100065836A1
• Filed: 12/23/2008
• Published: 03/18/2010
• Est. Priority Date: 09/18/2008
• Status: Abandoned Application

• Current Assignee: Hynix Semiconductor Incorporated (SK Hynix Inc.)
• Original Assignee: Hynix Semiconductor Incorporated (SK Hynix Inc.)
• Inventors: Lee, Yu-Jin
• Application Number:
  US12/342,774
• Publication Number:
  US 20100065836A1
• Time in Patent Office: Days
• US Class Current: 257/43
• CPC Class Codes: B82Y 10/00 Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic
• CPC Class Codes: H10N 70/063 by etching of pre-deposited switching material layers, e.g. lithography
• CPC Class Codes: H10N 70/20 Multistable switching devices, e.g. memristors
• CPC Class Codes: H10N 70/826 adapted for essentially vertical current flow, e.g. sandwich or pillar type devices
• CPC Class Codes: H10N 70/8418 adapted for focusing electric field or current, e.g. tip-shaped
• CPC Class Codes: H10N 70/8833 Binary metal oxides, e.g. TaOx
• CPC Class Codes: H10N 70/8836 Complex metal oxides, e.g. perovskites, spinels

Abstract

A resistive memory device includes an insulation layer over a substrate, a nanowire penetrating the insulation layer, a resistive layer formed over the insulation layer and contacting with the nanowire, and an upper electrode formed over the resistive layer.

Claims

1. A resistive memory device, comprising:

a substrate;

an insulation layer over the substrate;

a nanowire defining a lower electrode and penetrating the insulation layer;

a resistive layer formed over the insulation layer and contacting the nanowire; and

an upper electrode formed over the resistive layer.

2. The device of claim 1, wherein the resistive layer includes a binary oxide or a perovskite-based oxide.

3. The device of claim 1, wherein the nanowire includes a metal nanowire or a semiconductor nanowire.

4. The device of claim 1, wherein the nanowire includes a metal nanowire doped with impurity or a semiconductor nanowire doped with impurity.

5. The device of claim 1, wherein the nanowire includes a nanowire or a plurality of nanowires.

6. The device of claim 5, wherein a diameter of the nanowire ranges from approximately 1 nm to approximately 30 nm.

7. The device of claim 1, wherein the resistive layer has two different resistance states respectively corresponding to generation and disappearance of a filament current path in a portion of the resistive layer that contacts the nanowire, upon application of a voltage across the nanowire and the upper electrode.

8. The device of claim 1, wherein the substrate includes a selectable transistor or a selectable diode and the nanowire electrically contacts the selectable transistor or the selectable diode.

9. A method of fabricating a resistive memory device, the method comprising:

forming a nanowire penetrating an insulation layer over a substrate to define a lower electrode;

forming a resistive layer over the insulation layer to contact the nanowire; and

forming an upper electrode over the resistive layer.

10. The method of claim 9, wherein the resistive layer include a binary oxide or a perovskite-based oxide.

11. The method of claim 9, wherein the forming of the nanowire comprises:

forming a catalyst layer over the substrate in a region where the nanowire is to be formed;

growing the nanowire from the catalyst layer to obtain a first resultant structure;

forming the insulation layer over the first resultant structure including the grown nanowire to obtain a second resultant structure; and

partially removing the insulation layer from the second resultant structure to expose an upper portion of the nanowire;

wherein the resistive layer is formed over the insulation layer to contact the nanowire at said exposed upper portion.

12. The method of claim 11, wherein said partially removing comprises planarizing the second resultant structure.

13. The method of claim 11, wherein the forming of the catalyst layer over the substrate comprises:

depositing a catalyst material over the substrate; and

patterning the catalyst material to remain in the region where the nanowire is to be formed, thereby obtaining the catalyst layer.

14. The method of claim 11, wherein the forming of the catalyst layer over the substrate comprises:

forming a lower insulation layer over the substrate while exposing the substrate in the region where the nanowire is to be formed; and

forming the catalyst layer over the exposed region of the substrate.

15. The method of claim 11, wherein the catalyst layer comprises a metal layer.

16. The method of claim 11, wherein the catalyst layer has a thickness ranging from approximately 10 Å

to approximately 100 Å

.

17. A method of forming an electrode for a resistive memory device that comprises a resistive layer sandwiched between said electrode and another electrode, said method comprising:

forming a catalyst layer over a substrate in a region where said electrode is to be formed;

growing a nanowire from the catalyst layer to form said electrode; and

burying the nanowire in an insulation layer.

18. The method of claim 17, wherein said burying comprises

forming the insulation layer over a first resultant structure including the grown nanowire to obtain a second resultant structure;

and

partially removing the insulation layer from the second resultant structure to expose an upper portion of the nanowire where the resistive layer is to be formed over to contact the nanowire.

19. The method of claim 18, wherein said partially removing comprises planarizing the second resultant structure.

20. The method of claim 17, wherein the catalyst layer comprises a metal layer and has a thickness ranging from approximately 10 Å

to approximately 100 Å

.