THIN FILM TRANSISTOR ARRAY SUBSTRATE AND METHOD OF MANUFACTURING THE SAME

• US 20100065841A1
• Filed: 09/09/2009
• Published: 03/18/2010
• Est. Priority Date: 09/12/2008
• Status: Active Grant

• Current Assignee: Samsung Display Company Limited (Samsung Electronics Co. Ltd.)
• Original Assignee: Samsung Electronics Co. Ltd.
• Inventors: LEE, Je-Hun, KIM, Do-Hyun, YOON, Kap-Soo, KIM, Ki-Won, LEE, Woo-Geun
• Granted Patent: US 8,288,766 B2
• Time in Patent Office: Days
• US Class Current: 257/43
• CPC Class Codes: H01L 21/0214 the material being a silicon oxynitride, e.g. SiON or SiON:H
• CPC Class Codes: H01L 21/02164 the material being a silicon oxide, e.g. SiO2
• CPC Class Codes: H01L 21/0217 the material being a silicon nitride not containing oxygen, e.g. SixNy or SixByNz H01L21/02126 and H01L21/0214 take precedence
• CPC Class Codes: H01L 21/02554 Oxides
• CPC Class Codes: H01L 21/02565 Oxide semiconducting materials not being Group 12/16 materials, e.g. ternary compounds
• CPC Class Codes: H01L 23/53238 Additional layers associated with copper layers, e.g. adhesion, barrier, cladding layers
• CPC Class Codes: H01L 27/1225 with semiconductor materials not belonging to the group IV of the periodic table, e.g. InGaZnO
• CPC Class Codes: H01L 27/124 with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits wiring structures per se H01L23/52
• CPC Class Codes: H01L 27/1248 with a particular composition or shape of the interlayer dielectric specially adapted to the circuit arrangement
• CPC Class Codes: H01L 27/1262 with a particular formation, treatment or coating of the substrate
• CPC Class Codes: H01L 29/45 Ohmic electrodes
• CPC Class Codes: H01L 29/4908 for thin film semiconductor, e.g. gate of TFT
• CPC Class Codes: H01L 29/513 the variation being perpendicular to the channel plane
• CPC Class Codes: H01L 29/518 the insulating material containing nitrogen, e.g. nitride, oxynitride, nitrogen-doped material
• CPC Class Codes: H01L 29/66969 of devices having semiconductor bodies not comprising group 14 or group 13/15 materials comprising selenium or tellurium in uncombined form other than as impurities in semiconductor bodies of other materials, comprising cuprous oxide or cuprous iodide H01L21/02365
• CPC Class Codes: H01L 29/78603 characterised by the insulating substrate or support H01L29/78657 takes precedence
• CPC Class Codes: H01L 29/7869 having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

A TFT array substrate includes a semiconductive oxide layer disposed on an insulating substrate and including a channel portion, a gate electrode overlapping the semiconductive oxide layer, a gate insulating layer interposed between the semiconductive oxide layer and the gate electrode, and a passivation layer disposed on the semiconductive oxide layer and the gate electrode. At least one of the gate insulating layer and the passivation layer includes an oxynitride layer, and the oxynitride layer has a higher concentration of oxygen than that of nitrogen in a location of the oxynitride layer closer to the semiconductive oxide layer.

Claims

1. A thin film transistor array substrate comprising:

a semiconductive oxide layer disposed on an insulating substrate and including a channel portion;

a gate electrode overlapping the semiconductive oxide layer;

a gate insulating layer interposed between the semiconductive oxide layer and the gate electrode; and

a passivation layer disposed overlapping the semiconductive oxide layer and the gate electrode,

wherein at least one of the gate insulating layer and the passivation layer includes an oxynitride layer, the oxynitride layer having a higher concentration of oxygen than that of nitrogen in a location of the oxynitride layer closer to the semiconductive oxide layer.

2. The thin film transistor array substrate of claim 1, wherein the oxynitride layer comprises silicon oxynitride, aluminum oxynitride, titanium oxynitride, zirconium oxynitride, hafnium oxynitride, tantalum oxynitride, or tungsten oxynitride.

3. The TFT array substrate of claim 1, wherein the semiconductive oxide layer comprises an oxide selected from an element group consisting of Zn, In, Ga, Sn and combinations thereof.

4. The thin film transistor array substrate of claim 1, wherein

the gate insulating layer interposed between the semiconductive oxide layer and the gate electrode is disposed directly on and contacting the gate electrode, the gate electrode being disposed between the gate insulating layer and the insulating substrate,

the semiconductive oxide layer is disposed directly on and contacting the gate insulating layer interposed between the semiconductive oxide layer and the gate electrode, and

the passivation layer is disposed directly on and contacting the semiconductive oxide layer contacting the gate insulating layer.

5. The thin film transistor array substrate of claim 4, wherein the gate insulating layer and the passivation layer both include the oxynitride layer.

6. The thin film transistor array substrate of claim 1, wherein

the gate insulating layer interposed between the semiconductive oxide layer and the gate electrode is disposed directly on and contacting the semiconductive oxide layer,

the gate electrode is disposed directly on and contacting the gate insulating layer, the gate insulating layer being disposed between the gate electrode and the insulating substrate, and

the passivation layer is disposed directly on and contacting the gate electrode.

7. The thin film transistor array substrate of claim 6, wherein the gate insulating layer comprises an oxynitride layer.

8. A thin film transistor array substrate comprising:

a semiconductive oxide layer disposed on an insulating substrate and including a channel portion;

a gate electrode overlapping the semiconductive oxide layer;

a gate insulating layer interposed between the semiconductive oxide layer and the gate electrode; and

a passivation layer disposed on the semiconductive oxide layer and the gate electrode,

wherein at least one of the gate insulating layer and the passivation layer includes an oxide layer and a nitride layer which is separate from the oxide layer, the oxide layer contacting the semiconductive oxide layer, and the nitride layer not contacting the semiconductive oxide layer.

9. The thin film transistor array substrate of claim 8, wherein the oxide layer comprises silicon oxide, aluminum oxide, titanium oxide, zirconium oxide, hafnium oxide, tantalum oxide, or tungsten oxide.

10. The thin film transistor array substrate of claim 8, wherein the nitride layer comprises silicon nitride, aluminum nitride, titanium nitride, zirconium nitride, hafnium nitride, tantalum nitride, or tungsten nitride.

11. The thin film transistor array substrate of claim 8, wherein the semiconductive oxide layer comprises an oxide selected from an element group consisting of Zn, In, Ga, Sn and combinations thereof.

12. The thin film transistor array substrate of claim 8, wherein

the gate insulating layer interposed between the semiconductive oxide layer and the gate electrode is disposed directly on and contacting the gate electrode the gate electrode being disposed between the gate insulating layer and the insulating substrate,

the semiconductive oxide layer is disposed directly on and contacting the gate insulating layer interposed between the semiconductive oxide layer and the gate electrode, and

the passivation layer is disposed directly on and contacting the semiconductive oxide layer contacting the gate insulating layer.

13. The thin film transistor array substrate of claim 12, wherein the gate insulating layer includes a lower nitride layer and an upper oxide layer, and the passivation layer includes a lower oxide layer and an upper nitride layer.

14. The thin film transistor array substrate of claim 8, wherein

the gate insulating layer interposed between the semiconductive oxide layer and the gate electrode is disposed directly on and contacting the semiconductive oxide layer,

the gate electrode is disposed directly on and contacting the gate insulating layer, the gate insulating layer being disposed between the gate electrode and the insulating substrate, and

the passivation layer is disposed directly on and contacting the gate electrode.

15. The thin film transistor array substrate of claim 14, wherein the gate insulating layer includes a lower oxide layer and an upper nitride layer.

16. A method of manufacturing thin film transistor array substrate, the method comprising:

forming a gate electrode on an insulating substrate;

forming a gate insulating layer directly on the gate electrode;

forming a semiconductive oxide layer directly on and contacting the gate insulating layer, and overlapping the gate electrode;

forming a source electrode and a drain electrode separated from each other, and directly on the semiconductive oxide layer; and

forming a passivation layer directly on the source electrode and the drain electrode, and contacting the semiconductive oxide layer,

wherein at least one of the gate insulating layer and the passivation layer is formed including an oxynitride layer, the oxynitride layer having a higher concentration of oxygen than that of nitrogen in a location of the oxynitride layer closer to the semiconductive oxide layer.

17. The method of claim 16, wherein a gradation in the concentration of oxygen in the oxynitride layer is formed by adjusting a partial pressure of N₂O or O₂ as a source gas.

18. The method of claim 16, wherein the oxynitride layer is formed by depositing a nitride layer and an oxide layer respectively and then performing heat treatment.

19. The method of claim 16, wherein the gate insulating layer and the passivation layer are both formed including the oxynitride layer.

20. A method of manufacturing thin film transistor array substrate, the method comprising:

forming a gate electrode on an insulating substrate;

forming a gate insulating layer directly on the gate electrode;

forming a semiconductive oxide layer directly on and contacting the gate insulating layer, and overlapping the gate electrode;

forming a source electrode and a drain electrode separated from each other, and directly on the semiconductive oxide layer; and

forming a passivation layer directly on the source electrode and the drain electrode, and contacting the semiconductive layer,

wherein at least one of the gate insulating layer and the passivation layer comprises an oxide layer and a nitride layer which is separate from the oxide layer, the oxide layer contacting the semiconductive oxide layer, and the nitride layer not contacting the semiconductive oxide layer.

21. The method of claim 20, wherein the gate insulating layer includes a lower nitride layer and an upper oxide layer, and the passivation layer includes a lower oxide layer and an upper nitride layer.