SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF

• US 20100065842A1
• Filed: 09/10/2009
• Published: 03/18/2010
• Est. Priority Date: 09/12/2008
• Status: Active Grant

• Current Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Original Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Inventors: AKIMOTO, Kengo, YAMAZAKI, Shunpei, UOCHI, Hideki, KOMORI, Shigeki
• Granted Patent: US 8,501,555 B2
• Time in Patent Office: Days
• US Class Current: 257/43
• CPC Class Codes: H01L 27/1225 with semiconductor materials not belonging to the group IV of the periodic table, e.g. InGaZnO
• CPC Class Codes: H01L 27/124 with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits wiring structures per se H01L23/52
• CPC Class Codes: H01L 29/7869 having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate

Abstract

It is an object of the present invention to provide a thin film transistor in which an oxide semiconductor film containing indium (In), gallium (Ga), and zinc (Zn) is used and contact resistance of a source or a drain electrode layer is reduced, and a manufacturing method thereof. An IGZO layer is provided over the source electrode layer and the drain electrode layer, and source and drain regions having lower oxygen concentration than the IGZO semiconductor layer are intentionally provided between the source and drain electrode layers and the gate insulating layer, so that ohmic contact is made.

Claims

1. A semiconductor device comprising:

a gate electrode over an insulating surface;

a gate insulating layer over the gate electrode;

a source region and a drain region over the gate insulating layer;

a first metal layer over the source region;

a second metal layer over the drain region; and

a non-single-crystal oxide semiconductor layer over the gate insulating layer, the first metal layer and the second metal layer, the non-single-crystal oxide semiconductor layer overlapping the gate electrode,

wherein an oxygen concentration in the source region and the drain region is lower than an oxygen concentration in the non-single-crystal oxide semiconductor layer.

2. The semiconductor device according to claim 1, wherein each of the non-single-crystal oxide semiconductor layer, the source region, and the drain region is an oxide layer including indium, gallium, and zinc.

3. The semiconductor device according to claim 1, wherein a side face of the source region and a side face of the drain region are in contact with the non-single-crystal oxide semiconductor layer.

4. The semiconductor device according to claim 1, wherein the non-single-crystal oxide semiconductor layer is in contact with the gate insulating layer.

5. A semiconductor device comprising:

a gate electrode over an insulating surface;

a gate insulating layer over the gate electrode;

a first oxide layer including indium, gallium, and zinc over the gate insulating layer, the first oxide layer partially overlapping the gate electrode;

a second oxide layer including indium, gallium, and zinc over the gate insulating layer, the second oxide layer partially overlapping the gate electrode;

a first metal layer over the first oxide layer;

a second metal layer over the second oxide layer; and

a third oxide layer including indium, gallium, and zinc over the gate insulating layer, the first metal layer and the second metal layer, the third oxide layer overlapping the gate electrode,

wherein an oxygen concentration in the first oxide layer and the second oxide layer is lower than an oxygen concentration in the third oxide layer.

6. The semiconductor device according to claim 5, wherein the third oxide layer is a non-single-crystal oxide semiconductor layer.

7. The semiconductor device according to claim 5, wherein a side face of the first oxide layer and a side face of the second oxide layer are in contact with the third oxide layer.

8. The semiconductor device according to claim 5, wherein the third oxide layer is in contact with the gate insulating layer.

9. A semiconductor device comprising:

a gate electrode over an insulating surface;

a gate insulating layer over the gate electrode;

a first oxide layer including indium, gallium, and zinc over the gate insulating layer, the first oxide layer partially overlapping the gate electrode;

a second oxide layer including indium, gallium, and zinc over the gate insulating layer, the second oxide layer partially overlapping the gate electrode;

a first metal layer over the first oxide layer;

a second metal layer over the second oxide layer;

a third oxide layer including indium, gallium, and zinc over the gate insulating layer, the first metal layer and the second metal layer, the third oxide layer overlapping the gate electrode;

a protective insulating film over the gate insulating layer, the first metal layer, the second metal layer and the third oxide layer; and

a pixel electrode over the protective insulating film, the pixel electrode being electrically connected to the second metal layer,

wherein an oxygen concentration in the first oxide layer and the second oxide layer is lower than an oxygen concentration in the third oxide layer.

10. The semiconductor device according to claim 9, wherein the third oxide layer is a non-single-crystal oxide semiconductor layer.

11. The semiconductor device according to claim 9, wherein a side face of the first oxide layer and a side face of the second oxide layer are in contact with the third oxide layer.

12. The semiconductor device according to claim 9, wherein the third oxide layer is in contact with the gate insulating layer.

13. A method for manufacturing a semiconductor device comprising the steps of:

forming a gate electrode over an insulating surface;

forming a gate insulating layer over the gate electrode;

forming a source region, a drain region, a source electrode layer over the source region and a drain electrode layer over the drain region;

subjecting the gate insulating layer, the source electrode layer, and the drain electrode layer which are exposed, to plasma treatment; and

forming a non-single-crystal oxide semiconductor layer over the gate insulating layer without exposure to air after the subjecting the gate insulating layer to plasma treatment,

wherein the non-single-crystal oxide semiconductor layer overlaps with the gate electrode, and

wherein an oxygen concentration in the source region and the drain region is lower than an oxygen concentration in the non-single-crystal oxide semiconductor layer.

14. The method for manufacturing a semiconductor device according to claim 13, wherein each of the non-single-crystal oxide semiconductor layer, and the source region and the drain region is formed using an oxide layer including indium, gallium, and zinc by a sputtering method.

15. The method for manufacturing a semiconductor device according to claim 13, wherein the source region and the drain region are etched in a self-aligned manner with the source electrode layer and the drain electrode layer used as a mask.

16. The method for manufacturing a semiconductor device according to claim 13, wherein an argon gas or an oxygen gas are used for the plasma treatment.