Structures and Methods for Reducing Dopant Out-diffusion from Implant Regions in Power Devices

• US 20100065905A1
• Filed: 09/17/2008
• Published: 03/18/2010
• Est. Priority Date: 09/17/2008
• Status: Active Grant

• Current Assignee: Semiconductor Components Industries LLC (ON Semiconductor Corporation)
• Original Assignee: Fairchild Semiconductor Corporation (ON Semiconductor Corporation)
• Inventors: Pan, James
• Granted Patent: US 8,253,194 B2
• Time in Patent Office: Days
• US Class Current: 257/330
• CPC Class Codes: H01L 21/26506 in group IV semiconductors
• CPC Class Codes: H01L 21/26513 of electrically active species
• CPC Class Codes: H01L 29/0856 Source regions
• CPC Class Codes: H01L 29/1095 Body region, i.e. base region, of DMOS transistors or IGBTs cell layout H01L29/0696
• CPC Class Codes: H01L 29/161 including two or more of the elements provided for in group H01L29/16 , e.g. alloys H01L29/1604 takes precedence
• CPC Class Codes: H01L 29/407 Recessed field plates, e.g. trench field plates, buried field plates
• CPC Class Codes: H01L 29/41766 with at least part of the source or drain electrode having contact below the semiconductor surface, e.g. the source or drain electrode formed at least partially in a groove or with inclusions of conductor inside the semiconductor H01L29/41733 - H01L29/41758 take precedence
• CPC Class Codes: H01L 29/42368 the thickness being non-uniform
• CPC Class Codes: H01L 29/456 on silicon
• CPC Class Codes: H01L 29/66712 Vertical DMOS transistors, i.e. VDMOS transistors
• CPC Class Codes: H01L 29/66727 with a step of recessing the source electrode
• CPC Class Codes: H01L 29/66734 with a step of recessing the gate electrode, e.g. to form a trench gate electrode
• CPC Class Codes: H01L 29/7802 Vertical DMOS transistors, i.e. VDMOS transistors
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236

Abstract

A semiconductor structure comprises a drift region of a first conductivity type in a semiconductor region. A well region of a second conductivity type is over the drift region. A source region of the first conductivity type is in an upper portion of the well region. A heavy body region of the second conductivity type extends in the well region. The heavy body region has a higher doping concentration than the well region. A first diffusion barrier region at least partially surrounds the heavy body region. A gate electrode is insulated from the semiconductor region by a gate dielectric.

Claims

1. A semiconductor structure comprising:

a drift region of a first conductivity type in a semiconductor region;

a well region of a second conductivity type over the drift region;

a source region of the first conductivity type in an upper portion of the well region;

a heavy body region of the second conductivity type extending in the well region, the heavy body region having a higher doping concentration than the well region;

a first diffusion barrier region at least partially surrounding the heavy body region; and

a gate electrode insulated from the semiconductor region by a gate dielectric.

2. The semiconductor structure of claim 1 wherein the first diffusion barrier region comprises carbon.

3. The semiconductor structure of claim 1 further comprising:

a trench extending into the semiconductor region, wherein the gate electrode is in the trench and the gate dielectric extends along sidewalls and a bottom of the trench, and wherein the well region and the source region abut the sidewalls of the trench.

4. The semiconductor structure of claim 1 wherein the gate electrode is positioned over an upper surface of the semiconductor region and the gate dielectric extends between the gate electrode and the upper surface of the semiconductor region, and wherein the gate electrode overlaps the source region and the well region along a surface of the semiconductor region.

5. The semiconductor structure of claim 1 wherein the first diffusion barrier region at least partially overlaps the heavy body region.

6. The semiconductor structure of claim 1 wherein the first diffusion barrier region extends along sides and bottom of the heavy body region.

7. The semiconductor structure of claim 1 wherein the first diffusion barrier region is configured to minimize lateral diffusion of dopants from the heavy body region.

8. The semiconductor structure of claim 1 further comprising:

a second diffusion barrier region extending between the source region and the well region.

9. The semiconductor structure of claim 8 wherein the second diffusion barrier region comprises carbon.

10. The semiconductor structure of claim 8 wherein the second diffusion barrier region is configured to minimize out-diffusion of dopants from the source region.

11. A semiconductor structure comprising:

a drift region of a first conductivity type in a semiconductor region;

a well region of a second conductivity type over the drift region;

a source region of the first conductivity type in an upper portion of the well region;

a first diffusion barrier region extending between the source region and the well region;

a heavy body region of the second conductivity type extending in the well region, the heavy body region having a higher doping concentration than the well region; and

a gate electrode insulated from the semiconductor region by a gate dielectric.

12. The semiconductor structure of claim 11 wherein the first diffusion barrier region comprises carbon.

13. The semiconductor structure of claim 11 further comprising:

a trench extending into the semiconductor region, wherein the gate electrode is in the trench and the gate dielectric extends along sidewalls and a bottom of the trench, and wherein the well region and the source region are adjacent to the sidewalls of the trench.

14. The semiconductor structure of claim 11 wherein the gate electrode is positioned over an upper surface of the semiconductor region and the gate dielectric extends between the gate electrode and the upper surface of the semiconductor region, and wherein the gate electrode overlaps the source region and the well region along a surface of the semiconductor region.

15. The semiconductor structure of claim 11 wherein the first diffusion barrier region at least partially overlaps the source region.

16. The semiconductor structure of claim 11 wherein the first diffusion barrier region is configured to minimize down-diffusion of dopants from the source region.

17. A method of forming a semiconductor structure, the method comprising:

forming a well region of a first conductivity type in a semiconductor region;

forming a source region of the second conductivity type in an upper portion of the well region;

forming a heavy body region of the first conductivity type in the well region, the heavy body region having a higher doping concentration than the well region;

forming a first diffusion barrier region in the well region;

forming a gate electrode; and

forming a gate dielectric extending between the gate electrode and the semiconductor region, wherein the first diffusion barrier layer at least partially surrounds the heavy body region.

18. The method of claim 17 wherein the first diffusion barrier region comprises carbon.

19. The method of claim 17 further comprising:

forming a trench extending into the semiconductor region, wherein the gate electrode is in the trench and the gate dielectric extends along sidewalls and a bottom of the trench, and wherein the well region and the source region are adjacent to the sidewalls of the trench.

20. The method of claim 17 wherein the gate electrode is positioned over an upper surface of the semiconductor region and the gate dielectric extends between the gate electrode and the upper surface of the semiconductor region, and wherein the gate electrode overlaps the source region and the well region along a surface of the semiconductor region.

21. The method of claim 17 wherein the first diffusion barrier region at least partially overlaps the heavy body region.

22. The method of claim 17 wherein the first diffusion barrier region extends along sides and bottom of the heavy body region.

23. The method of claim 17 further comprising:

forming a second diffusion barrier region, wherein the second diffusion barrier region extends between the source region and the well region.

24. The method of claim 23 wherein the first diffusion barrier region and the second diffusion barrier region comprise carbon.

25. A method of forming a semiconductor structure, the method comprising:

forming a drift region of a first conductivity type in a semiconductor region;

forming a well region of a second conductivity type over the drift region;

forming a source region of the first conductivity type in an upper portion of the well region;

forming a first diffusion barrier region in the well region;

forming a heavy body region of the second conductivity type in the well region, the heavy body region having a higher doping concentration than the well region;

forming a gate electrode; and

forming a gate dielectric, the gate dielectric insulating the gate electrode from the semiconductor region, wherein the first diffusion barrier region extends between the source region and the well region.

26. The method of claim 25 wherein the first diffusion barrier region comprises carbon.

27. The method of claim 25 further comprising:

forming a trench extending into the semiconductor region, wherein the gate electrode is in the trench and the gate dielectric extends along sidewalls and a bottom of the trench, and wherein the well region and the source region are adjacent to the sidewalls of the trench.

28. The method of claim 25 wherein the gate electrode is positioned over an upper surface of the semiconductor region and the gate dielectric extends between the gate electrode and the upper surface of the semiconductor region, and wherein the gate electrode overlaps the source region and the well region along a surface of the semiconductor region.

29. The method of claim 25 wherein the first diffusion barrier region at least partially overlaps the source region.