Semiconductor Devices Including Multiple Stress Films in Interface Area

• US 20100065919A1
• Filed: 11/18/2009
• Published: 03/18/2010
• Est. Priority Date: 09/28/2006
• Status: Active Grant

• Current Assignee: Hong-Jae Shin, Jae-Ouk Choo, Ki-Chul Kim, Nae-In Lee, Seo-Woo Nam, Young-Joon Moon
• Original Assignee: Hong-Jae Shin, Jae-Ouk Choo, Ki-Chul Kim, Nae-In Lee, Seo-Woo Nam, Young-Joon Moon
• Inventors: Nam, Seo-woo, Moon, Young-joon, Lee, Nae-in, Choo, Jae-ouk, Shin, Hong-jae, Kim, Ki-chul
• Granted Patent: US 7,902,609 B2
• Time in Patent Office: Days
• US Class Current: 257/369
• CPC Class Codes: H01L 21/823412 with a particular manufacturing method of the channel structures, e.g. channel implants, halo or pocket implants, or channel materials
• CPC Class Codes: H01L 21/823807 with a particular manufacturing method of the channel structures, e.g. channel implants, halo or pocket implants, or channel materials
• CPC Class Codes: H01L 27/088 the components being field-effect transistors with insulated gate
• CPC Class Codes: H01L 27/092 complementary MIS field-effect transistors
• CPC Class Codes: H01L 29/665 using self aligned silicidation, i.e. salicide formation of conductive layers comprising silicides H01L21/28518
• CPC Class Codes: H01L 29/6659 with both lightly doped source and drain extensions and source and drain self-aligned to the sides of the gate, e.g. lightly doped drain [LDD] MOSFET, double diffused drain [DDD] MOSFET
• CPC Class Codes: H01L 29/7843 the means being an applied insulating layer
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

A semiconductor substrate includes a first transistor area having a first gate electrode and first source/drain areas, a second transistor area having a second gate electrode and second source/drain areas, and an interface area provided at an interface of the first transistor area and the second transistor area and having a third gate electrode. A first stress film is on the first gate electrode and the first source/drain areas of the first transistor area and at least a portion of the third gate electrode of the interface area. A second stress film is on the second gate electrode and the second source/drain areas of the second transistor area and not overlapping the first stress film on the third gate electrode of the interface area or overlapping at least a portion of the first stress film. The second stress film overlapping at least the portion of the first stress film is thinner than the second stress film in the second transistor area. Related methods are also described.

Claims

1. A semiconductor device comprising:

a semiconductor substrate including a first transistor area having a first gate electrode and first source/drain areas, a second transistor area having a second gate electrode and second source/drain areas and an interface area provided at an interface between the first transistor area and the second transistor area and having a third gate electrode;

a first stress film on the first gate electrode and the first source/drain areas of the first transistor area and on at least a portion of the third gate electrode of the interface area; and

a second stress film on the second gate electrode and the second source/drain areas of the second transistor area and on at least a portion of the third gate electrode of the interface area, and not overlapping the first stress film on the third gate electrode of the interface area or overlapping at least a portion of the first stress film,

wherein the second stress film overlapping at least the portion of the first stress film is thinner than the second stress film in the second transistor area.

2. The semiconductor device of claim 1, further comprising:

a first interlayer insulating film on the first and the second stress films and

a second interlayer insulating film on the first interlayer insulating film;

wherein an interface between the first interlayer insulating film and the second interlayer insulating film is farther from the substrate than the first stress film on the third gate electrode or than the second stress film overlapping at least a portion of the first stress film.

3. The semiconductor device of claim 2, wherein the first and the second interlayer insulating films comprise O₃-TEOS, USG, PSG, BSG, BPSG, FSG, SOG and/or TOSZ.

4. The semiconductor device of claim 1, further comprising:

an etch stop film on the first stress film.

5. The semiconductor device of claim 4, wherein the etch stop film is an LTO film.

6. The semiconductor device of claim 1, wherein:

the first transistor area includes an NMOS transistor; and

the second transistor area includes a PMOS transistor.

7. The semiconductor device of claim 1, wherein:

the first stress film has tensile stress of about 0.01 to about 5 GPa; and

the second stress film has compressive stress of about −

0.01 to about −

5 GPa.

8. The semiconductor device of claim 1, further comprising silicide films on the first, the second, and the third gate electrodes, and on the first and the second source/drain areas.

9. The semiconductor device of claim 1, wherein the first stress film and the second stress film comprise SiN, SiON, SiBN, SiC, SiC:

H, SiCOH, SiCN and/or SiO₂.

10. The semiconductor device of claim 1, further comprising:

a plurality of contact holes through which the first, the second, and the third gate electrodes and the first and the second source/drain areas are exposed; and

a contact plug in a respective contact hole.

11. The semiconductor device of claim 1 wherein the second stress film abuts against but does not overlap the first stress film on the third gate electrode of the interface area.

12. The semiconductor device of claim 1 wherein the second stress film overlaps the first stress film on at least a portion of a top of the third gate electrode that is remote from the semiconductor substrate and wherein the second stress film is thinner on the top of the third gate electrode than in the second transistor area.

13. The semiconductor device of claim 1 wherein the second stress film is thinner on the top of the third gate electrode than on a sidewall of the third gate electrode.