SEMICONDUCTOR DEVICE WITH DECOUPLING CAPACITOR DESIGN

• US 20100065944A1
• Filed: 09/17/2008
• Published: 03/18/2010
• Est. Priority Date: 09/17/2008
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Chu, Huey-Chi, Ching, Kuo-Cheng, TU, Kuo-Chi
• Granted Patent: US 8,436,408 B2
• Time in Patent Office: Days
• US Class Current: 257/532
• CPC Class Codes: H01L 23/5223 Capacitor integral with wiring layers
• CPC Class Codes: H01L 27/0629 in combination with diodes, or resistors, or capacitors
• CPC Class Codes: H01L 28/40 Capacitors
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
• CPC Class Codes: H10B 12/033 the capacitor extending over the transistor
• CPC Class Codes: H10B 12/09 with simultaneous manufacture of the peripheral circuit region and memory cells

Abstract

An integrated circuit includes a circuit module having a plurality of active components coupled between a pair of supply nodes, and a capacitive decoupling module coupled to the circuit module. The capacitive decoupling module includes a plurality of metal-insulator-metal (MiM) capacitors coupled in series between the pair of supply nodes, wherein a voltage between the supply nodes is divided across the plurality of MiM capacitors, thereby reducing voltage stress on the capacitors.

Claims

1. An integrated circuit comprising:

a circuit module having a plurality of active components coupled between a pair of supply nodes; and

a capacitive decoupling module coupled to the circuit module, the capacitive decoupling module comprising a plurality of metal-insulator-metal (MiM) capacitors coupled in series between the pair of supply nodes, wherein a voltage between said supply nodes is divided across said plurality of MiM capacitors, thereby reducing voltage stress on said capacitors.

2. The integrated circuit of claim 1, wherein the circuit module comprises a memory array.

3. The integrated circuit of claim 2, wherein the memory array is a DRAM cell array.

4. The integrated circuit of claim 1, wherein each of the MiM capacitors is formed in parallel with a respective resistor.

5. The integrated circuit of claim 4, wherein the resistors are polysilicon resistors.

6. The integrated circuit of claim 1,

wherein the decoupling capacitors are formed in a dielectric layer formed between a device substrate and a metal interconnect layer formed thereover having interconnects providing said supply nodes, and

wherein a bottom electrode of each of the decoupling capacitors is coupled to the metal interconnect layer at least in part through a respective lateral conductor formed on the device substrate.

7. The integrated circuit of claim 6, wherein said respective lateral conductors are coupled to the bottom electrodes of the decoupling capacitors and to the metal interconnect layer through conductive vias formed in said dielectric layer.

8. The integrated circuit of claim 6, wherein each of said respective lateral conductors comprises a polysilicon layer having a silicide layer formed thereon, wherein said silicide layers are coupled to the bottom electrodes of said decoupling capacitors and to said metal interconnect layer through conductive vias formed in said dielectric layer.

9. The integrated circuit of claim 8, wherein said conductors are formed over a shallow trench isolation formed in said device substrate.

10. The integrated circuit of claim 6, wherein each of the respective lateral conductors comprises a silicide pad layer formed on said device substrate, said respective lateral conductors being isolated from one another by an isolation region formed therebetween.

11. The integrated circuit of claim 6, wherein each of the respective lateral conductors comprises a contact plug formed between the device substrate and the decoupling capacitors, wherein the bottom electrodes of said decoupling capacitors are in contact with said contact plugs and said contact plugs are coupled to said metal interconnect layer through conductive vias formed in said dielectric layer.

12. The integrated circuit of claim 11, wherein the contact plugs are formed on respective silicide pad layers formed at the upper surface of said device substrate, wherein said respective silicide pad layers are isolated from one another by an isolation region formed therebetween.

13. The integrated circuit of claim 1, wherein the plurality of decoupling capacitors consists of two decoupling capacitors.

14. The integrated circuit of claim 1, wherein the plurality of decoupling capacitors comprises three or more decoupling capacitors.

15. An integrated circuit comprising:

one or more circuit modules;

one or more capacitive decoupling modules coupled to the one or more circuit modules, wherein each decoupling module includes;

a first node coupled to a first circuit connection point of the circuit modules;

a second node coupled to a second circuit module connection point of the circuit modules; and

a plurality of metal-insulator-metal (MiM) capacitors coupled in series between the first and second nodes, thereby dividing the voltage difference between said first and second nodes across said plurality of MiM capacitors and reducing voltage stress on said capacitors.

16. The integrated circuit of claim 15, wherein the first node is coupled to a first power level and the second node is coupled to a second power level.

17. The integrated circuit of claim 16, wherein the first power level is a positive power supply voltage and said second power level is ground.

18. The integrated circuit of claim 15, wherein the circuit modules comprise an embedded DRAM cell array.

19. The integrated circuit of claim 15, further comprising a respective polysilicon resistor formed in parallel with each of said MiM capacitors.

20. The integrated circuit of claim 15, wherein a bottom electrode of each of said MiM capacitors is coupled to a respective silicide region that is electrically coupled to a

first metal interconnect layer formed over the MiM capacitors.