PACKAGING STRUCTURE, PACKAGING METHOD AND PHOTOSENSITIVE DEVICE

• US 20100065956A1
• Filed: 03/27/2009
• Published: 03/18/2010
• Est. Priority Date: 09/12/2008
• Status: Abandoned Application

• Current Assignee: China Wafer Level CSP Co., Ltd.
• Original Assignee: China Wafer Level CSP Co., Ltd.
• Inventors: WANG, Zhiqi, Zou, Qiuhong, Wang, Wei, Yu, Guoqing
• Application Number:
  US12/412,778
• Publication Number:
  US 20100065956A1
• Time in Patent Office: Days
• US Class Current: 257/690
• CPC Class Codes: H01L 2224/02371 connecting the bonding area on a surface of the semiconductor or solid-state body with another surface of the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/02377 Fan-in arrangement
• CPC Class Codes: H01L 2224/05001 Internal layers
• CPC Class Codes: H01L 2224/05008 Bonding area integrally formed with a redistribution layer on the semiconductor or solid-state body, e.g.
• CPC Class Codes: H01L 2224/05099 Material
• CPC Class Codes: H01L 2224/05548 Bonding area integrally formed with a redistribution layer on the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/05569 the external layer being disposed on a redistribution layer on the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/05624 Aluminium [Al] as principal constituent
• CPC Class Codes: H01L 2224/05644 Gold [Au] as principal constituent
• CPC Class Codes: H01L 2224/05655 Nickel [Ni] as principal constituent
• CPC Class Codes: H01L 2224/13024 the bump connector being disposed on a redistribution layer on the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/131 with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
• CPC Class Codes: H01L 24/05 of an individual bonding area
• CPC Class Codes: H01L 24/13 of an individual bump connector
• CPC Class Codes: H01L 24/16 of an individual bump connector
• CPC Class Codes: H01L 27/14618 Containers
• CPC Class Codes: H01L 27/14627 Microlenses
• CPC Class Codes: H01L 27/14636 Interconnect structures
• CPC Class Codes: H01L 27/14683 Processes or apparatus peculiar to the manufacture or treatment of these devices or parts thereof not peculiar thereto H01L21/00
• CPC Class Codes: H01L 27/14685 Process for coatings or optical elements
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01028 : Nickel [Ni]
• CPC Class Codes: H01L 2924/01079 : Gold [Au]
• CPC Class Codes: H01L 2924/014 : Solder alloys
• CPC Class Codes: H01L 2924/14 : Integrated circuits
• CPC Class Codes: H01L 2924/3025 : Electromagnetic shielding
• CPC Class Codes: H01L 31/0203 : Containers; Encapsulations , e.g. encapsulation of photodiodesfor photovoltaic devices H01L31/048; for organic photosensitive devices H10K30/80
• CPC Class Codes: H01L 31/0232 : Optical elements or arrangements associated with the device H01L31/0236 takes precedence; for photovoltaic cells H01L31/054; for photovoltaic modules H02S40/20

Abstract

The application provides a packaging structure, a packaging method and a photosensitive device. The packaging structure includes a substrate structure, a chip and a solder bump electrically connecting with a pad on the chip. The solder bump is located on the substrate structure, so that the multilayer coverage structure required when forming a bump on a side of the chip in the prior art packaging structure is avoided. In this way, the thickness of the packaging structure is reduced and the reliably of the packaging structure is improved.

Claims

1. A packaging structure, comprising a substrate structure, a chip, and a solder bump electrically connected to a pad on the chip, wherein the solder bump is located on the substrate structure.

2. The packaging structure according to claim 1, wherein the solder bump is located on a surface of the substrate structure which is distant from the chip.

3. The packaging structure according to claim 1, further comprising a conductive layer connected to the solder bump and the pad.

4. The packaging structure according to claim 3, wherein the pad is totally or partly covered by the conductive layer.

5. The packaging structure according to claim 3, wherein the conductive layer is made of a metal or Indium Tin Oxides (ITO).

6. The packaging structure according to claim 1, further comprising a protection layer located on a side of the chip which is distant from the substrate structure.

7. The packaging structure according to claim 1, wherein a device to be sealed is configured on a functional side of the chip, the substrate structure comprises a substrate and a cavity wall, the substrate, the cavity wall and the chip form a cavity which seals the device therein and leaves the pad outside the cavity.

8. The packaging structure according to claim 7, wherein the device comprises an optical sensor and orthogonal projections of the solder bump and the conductive layer on the chip are separated from the optical sensor.

9. The packaging structure according to claim 7, wherein the substrate is made of glass.

10. The packaging structure according to claim 7, wherein an angle formed between a surface of the substrate which is opposite to the chip and a sidewall of the substrate is an acute angle.

19. A photosensitive device comprising a packaging structure according to claim 1, a lens and a Printed Circuit Board (PCB), wherein the PCB is connected to a bump on the packaging structure and is located between the lens and the packaging structure.

11. A packaging method, comprising:

providing a half-finished packaging structure comprising a substrate structure and a chip having an exposed pad thereon; and

forming a solder bump electrically connected with the pad on a surface of the substrate structure in the packaging structure.

12. The packaging method according to claim 11, wherein the solder bump is formed on a surface of the substrate structure which is distant from the chip.

13. The packaging method according to claim 11, wherein the pad is electrically connected to the solder bump via a conductive layer formed between the pad and the solder bump on the substrate structure.

14. The packaging method according to claim 13, wherein by totally or partly covering the pad, the conductive layer is connected to the pad.

15. The packaging method according to claim 11, further comprising:

forming a protection layer on a side of the chip which is distant from the substrate structure.

16. The packaging method according to claim 11, wherein forming the half-finished packaging structure comprises:

Providing the substrate structure comprising a substrate and a ring-like cavity wall on the substrate;

Providing the chip comprising a functional side on which a device to be sealed and a pad located in exterior of an area enclosing the device on the functional side are configured;

Forming an adhesive layer on a side of the ring-like cavity wall which is distant from the substrate;

Adhering the chip to the substrate structure so that the substrate, the cavity wall and the chip form a cavity which seals the device therein and leaves the pad outside the cavity.

17. The packaging method according to claim 16, wherein the device comprises an optical sensor and orthogonal projections of the solder bump and the conductive layer on the chip are separated from the optical sensor.

18. The packaging structure according to claim 16, wherein the substrate is made of glass.