PARALLEL-PLATE STRUCTURE FABRICATION METHOD AND PARALLEL-PLATE STRUCTURE ARRANGEMENT

• US 20100067167A1
• Filed: 09/14/2007
• Published: 03/18/2010
• Est. Priority Date: 09/18/2006
• Status: Active Grant

• Current Assignee: Valtion Teknillinen Tutkimuskeskus
• Original Assignee: Valtion Teknillinen Tutkimuskeskus
• Inventors: Riekkinen, Tommi, Mattila, Tomi
• Granted Patent: US 8,950,057 B2
• Time in Patent Office: Days
• US Class Current: 361/281
• CPC Class Codes: H01G 7/06 having a dielectric selected for the variation of its permittivity with applied voltage, i.e. ferroelectric capacitors electrets H01G7/02
• CPC Class Codes: H01L 28/55 with a dielectric comprising a perovskite structure material
• CPC Class Codes: H10N 30/06 Forming electrodes or interconnections, e.g. leads or terminals
• CPC Class Codes: H10N 30/072 by laminating or bonding of piezoelectric or electrostrictive bodies
• CPC Class Codes: H10N 30/8536 Alkaline earth metal based oxides, e.g. barium titanates
• CPC Class Codes: Y10T 29/42 Piezoelectric device making
• CPC Class Codes: Y10T 29/435 Solid dielectric type
• CPC Class Codes: Y10T 29/49002 Electrical device making

Abstract

A fabrication method for parallel-plate structures and a parallel-plate structure arrangement, wherein the structures have a middle layer, grown on a substrate and disposed between top and bottom electrode layers, wherein the middle layer and the top and bottom electrode layers are deposited on a bottom substrate, and wherein the middle layer is grown first and the top and bottom electrodes are essentially deposited afterwards.

Claims

1. A fabrication method for parallel-plate structures,

wherein the structures have a middle layer, grown on a substrate and disposed between top and bottom electrode layers,

wherein the middle layer and the top and bottom electrode layers are deposited on a bottom substrate,

characterized in that in the method

the middle layer is grown first and the top and bottom electrodes are essentially deposited afterwards.

2. The method according to claim 1, characterized in that in the method:

the middle layer is first grown on a first substrate,

the bottom electrode is deposited after the middle layer growth,

the layer stack is transferred to a second substrate,

the first substrate is removed, and

the top electrode is deposited on top of the middle layer.

3. The method according to claim 1, characterized in that the processing conditions for optimal middle layer growth are destructive for opti-mal electrode materials.

4. The method according to claim 1, characterized in that the middle layer is ceramic material, such as metal oxide, metal nitride, metal fluoride, featuring ferroelectric, paraelectric or piezoelectric properties or a com-bination of those.

5. The method according to claim 1, characterized in that the middle layer is perovskite material such as Ba_xSr_1-xTiO₃, or piezoelectric material such as ZnO, AlN.

6. The method according to claim 1, characterised in that the middle layer is a stack of layers made of materials in claims 4 and 5.

7. The method according to claim 1, characterised in that the bottom and the top electrodes are of electrically conductive material.

8. The method according to claim 1, characterised in that the bottom and the top electrodes are metal, such as Cu, Al, Au, Ag, Pt.

9. The method according to claim 1, characterised in that adhesion layers and/or diffusion barriers are applied between the bottom and top electrodes and the middle layer.

10. The method according to claim 1, characterised in that in the bottom and/or top electrodes are/is patterned.

11. The method according to claim 1, characterised in that a buffer layer is deposited and suitably processed (e.g. ground and polished) in order to allow wafer bonding to a second (bottom) substrate.

12. The method according to claim 1, characterised in that the prepared first wafer, on which the middle layer and the bottom electrode reside, is bonded with the second substrate, and that after bonding, the first substrate is removed.

13. The method according to claim 12, characterised in that in removal of the first substrate is implemented

etch selectively:

(a) etch stop after first substrate is removed, and (b) the second substrate and the middle layer are selective to the first substrate removal or are protected,

or by chemical-mechanical thinning (grinding, polishing) followed by plasma etching (e.g ICP, DRIE).

14. The method according to claim 1, characterised in that the middle layer compound is patterned before or after wafer bonding.

15. The method according to claim 14, characterized in that the patterning is implemented for ohmic contact creation to the bottom metal electrode from the top metal electrode.

16. The method according to claim 1, characterized in that the electrodeposition growth is applied to obtain thick top metal conductors.

17. A parallel-plate structure arrangement obtainable by a fabrication method, wherein the structures have a middle layer grown on a substrate and disposed between top and bottom electrode layers, wherein the middle layer and the top and bottom electrode layers are deposited on a bottom substrate, characterized in that in the method the middle layer is grown first and the top and bottom electrodes are essentially deposited afterwards.

18. The arrangement according to claim 17, characterized in that in the method:

the middle layer is first grown on a first substrate,

the bottom electrode is deposited after the middle layer growth,

the layer stack is transferred to a second substrate,

the first substrate is removed, and

the top electrode is deposited on top of the middle layer.

19. The arrangement according to claim 17, characterized in that the processing conditions for optimal middle layer growth are destructive for optimal electrode materials.

20. The arrangement according to claim 17, characterized in that the middle layer is ceramic material, such as metal oxide, metal ni-tride, metal fluoride, featuring ferroelectric, paraelectric or piezoelectric properties or a combination of those.

21. The arrangement according to claim 17, characterized in that the middle layer is perovskite material such as Ba_xSr—

I—

XTiO₃, or piezoelectric material such as ZnO, AIN.

22. The arrangement according to claim 17, characterized in that the middle layer is a stack of layers made of materials in claims 20 and 21.

23. The arrangement according to claim 17, characterized in that the bottom and the top electrodes are of electrically conductive material.

24. The arrangement according to claim 17, characterized in that the bottom and the top electrodes are metal, such as Cu, Al, Au, Ag, Pt.

25. The arrangement according to claim 17, characterized in that adhesion layers and/or diffusion barriers are applied between the bottom and top electrodes and the middle layer.

26. The arrangement according to claim 17, characterized in that in the bottom and/or top electrodes are/is patterned.

27. The arrangement according to claim 17, characterized in that a buffer layer is deposited in order to allow wafer bonding to a second (bottom) substrate.

28. The arrangement according to claim 17, characterized in that the prepared first wafer, on which the middle layer and the bottom electrode reside, is bonded with the second substrate, and that after bonding, the first substrate is removed.

29. The arrangement according to claim 17, characterized in that in removal of the first substrate is implemented

etch selectively:

(a) etch stop after first substrate is removed, and (b) the second substrate and the middle layer are selective to the first substrate removal or are protected, or

by chemical-mechanical thinning (grinding, polishing) followed by plasma etching (e.g ICP, DRIE).

30. The arrangement according to claim 17, characterized in that the middle layer compound is patterned before or after wafer bonding.

31. The arrangement according to claim 30, characterized in that the patterning is implemented for ohmic contact creation to the bottom metal electrode from the top metal electrode.

32. The arrangement according to claim 17, characterized in that electrodeposition is applied to obtain thick top metal conductors.

33. The arrangement according to claim 17, characterized in that the structure is a capacitor arrangement.

34. The arrangement according to claim 17, characterized in that the second substrate is glass or similar insulating material featuring low RF-losses.

35. The arrangement according to claim 17, characterized in that the arrangement forms an integrated structure, whereby the structure or structures are applied to small areas on a larger substrate area, and that the same wafers include additional integrated components such as (i) several inductors or further capacitors, (ii) resistors (e.g. for biasing), (iii) non-tunable capacitors.

36. The arrangement according to claim 31, characterized in that the top electrode includes a contact to the bottom electrode, whereby a structure is formed between the top and bottom layers wherein further the bottom electrode is connected to another area on the top layer in order to get an external contact.

37. The arrangement according to claim 17, characterized in a structure where a DC contact is realized to the bottom electrode, whereby the bottom electrode connects the two ferroelectric structures in series.

38. The arrangement according to claim 37, characterized in that by connecting a tuning DC voltage to the bottom electrode, the two structures will be inversely biased.

39. The arrangement according to claim 32, characterized in that the thick top metal layer is provided with a low-loss inductor, which is connected with the dual inversely biased structure.

40. The arrangement according to claim 32, characterized in that the structure includes a first capacitor structure, a low-loss inductor, and a second capacitor structure.

41. The arrangement according to claim 17, characterized in that the capacitor(s) is/are tunable.

42. The arrangement according to claim 17, characterized in that an additional layer or additional layers serving as adhesion layer(s) and/or diffusion barrier(s) is/are employed (e.g. TiW) between the middle, top and/or the bottom electrodes.

43. The method according to claim 1, characterized in that the processed structure or part of the structure exhibits acoustic wave resonances and is operated as a FBAR (Thin Film Bulk Acoustic Resonator) or as a TFBAR (Tunable Thin Film Bulk Acoustic Resonator).

44. The arrangement according to claim 17, characterized in that the processed structure or part of the structure exhibits acoustic wave resonances and is operated as a FBAR (Thin Film Bulk Acoustic Resonator) or as a TFBAR (Tunable Thin Film Bulk Acoustic Resonator).

45. The method according to claim 1, characterized in that the processed structure additional layer or layers are deposited acting as acoustic mirror(s).

46. The arrangement according to claim 17, characterized in that the processed structure contains additional layer or layers acting as acoustic mirror(s).