METHOD OF COMMUNICATION BETWEEN A PROTOCOL-PROCESSING UNIT AND AN INPUT/OUTPUT (I/O) DEVICE THROUGH A DEVICE INTERFACE CONTROLLER

• US 20100070658A1
• Filed: 09/09/2009
• Published: 03/18/2010
• Est. Priority Date: 09/12/2008
• Status: Abandoned Application

• Current Assignee: Weltrend Semiconductor Inc.
• Original Assignee: Etrend Electronics, Inc.
• Inventors: Wu, Ming-Feng, Tsai, Chang-Ming, Chiang, Hung-Chih, Liu, Yau-Wen, Cheng, Chi-Cheng, Hsiao, Shih-Ching
• Application Number:
  US12/555,869
• Publication Number:
  US 20100070658A1
• Time in Patent Office: Days
• US Class Current: 710/13
• CPC Class Codes: G06F 12/0868 Data transfer between cache memory and other subsystems, e.g. storage devices or host systems
• CPC Class Codes: G06F 13/385 for adaptation of a particular data processing system to different peripheral devices
• CPC Class Codes: G06F 2212/311 In host system

Abstract

A method of communication between a protocol-processing unit and an input/output (I/O) device through a device interface controller includes configuring the protocol-processing unit to write command/message data in a predefined write file, and configuring the device interface controller to translate the command/message data written in the predefined write file into a corresponding command/message and to transmit the corresponding command/message thus translated to the I/O device. A system that includes the protocol-processing unit and the device interface controller is also disclosed.

Claims

1. A method of communication between a protocol-processing unit and an input/output (I/o) device through a device interface controller, said method comprising:

A) configuring the protocol-processing unit to write command/message data in a predefined write file; and

B) configuring the device interface controller to translate the command/message data written in the predefined write file into a corresponding command/message and to transmit the corresponding command/message thus translated to the I/O device.

2. The method as claimed in claim 1, further comprising:

C) configuring the protocol-processing unit to transfer the command/message data written in step A) from a cache memory to the device interface controller prior to step B).

3. The method as claimed in claim 1, further comprising:

C) configuring the protocol-processing unit to disable a cache memory prior to step A).

4. The method as claimed in claim 1, wherein step B) is performed only when, in step A), the command/message data is written in the predefined write file.

5. The method as claimed in claim 1, wherein step A) is performed in one of a filename access mode, where the command/message data is written in the predefined write file with reference to a filename of the predefined write file, and a logical address access mode, where the command/message data is written in the predefined write file with reference to a logical address of the predefined write file.

6. The method as claimed in claim 1, further comprising:

C) configuring the device interface controller to receive a result from the I/O device;

D) configuring the protocol-processing unit to read a response data from a predefined read file; and

E) configuring the device interface controller to translate the result into the response data, and to transmit the response data thus translated to the protocol-processing unit.

7. The method as claimed in claim 6, wherein step E) is performed only when, in step D), the response data is read from the predefined read file.

8. The method as claimed in claim 6, further comprising:

F) configuring the protocol-processing unit to disable a cache memory prior to step D).

9. The method as claimed in claim 6, wherein the protocol-processing unit is configured to read data, the size of which is larger than that of a cache memory, prior to step D), thereby permitting the protocol-processing unit to read the response data from the device interface controller and not from the cache memory.

10. The method as claimed in claim 6, wherein the protocol-processing unit is configured to read a plurality of offset sectors of the predefined read file prior to step D), thereby permitting the protocol-processing unit to read the response data from the device interface controller and not from a cache memory.

11. The method as claimed in claim 10, wherein the protocol-processing unit is configured to read the offset sectors of the predefined read file in one of an incrementing manner and a decrementing manner.

12. The method as claimed in claim 6, wherein the protocol-processing unit is configured to read data in an accumulative manner prior to step D), thereby permitting the protocol-processing unit to read the response data from the device interface controller and not from a cache memory.

13. The method as claimed in claim 6, wherein step D) is performed in one of a filename access mode, where the response data is read from the predefined read file with reference to a filename of the predefined read file, and a logical address access mode, where the response data is read from the predefined read file with reference to a logical address of the predefined read file.

14. The method as claimed in claim 6, wherein the predefined write and read files are the same file.

15. The method as claimed in claim 6, wherein the predefined write and read files are different files.

16. The method as claimed in claim 6, further comprising:

F) configuring the device interface controller to serve as a virtual memory with a file format architecture, which includes the predefined read and write files, when there is no flash memory connected thereto.

17. The method as claimed in claim 1, wherein the device interface controller is connected to the protocol-processing unit via a device interface that complies with a standard established for small form memory card interface.

18. The method as claimed in claim 17, wherein the device interface is one of a secure digital (SD) memory card compliant interface, a multimedia card (MMC) memory card compliant interface, a memory stick (MS) memory card compliant interface, and a MS micro (M2) memory card compliant interface.

19. A system, comprising:

a protocol-processing unit; and

a device interface controller coupled to said protocol-processing unit and adapted to be coupled to an I/O device,

wherein said protocol-processing unit is operable so as to write command/message data in a predefined write file, and

wherein said device interface controller is operable so as to translate the command/message data written in the predefined write file into a corresponding command/message and so as to transmit the corresponding command/message thus translated to the I/O device.

20. The system as claimed in claim 19, wherein said protocol-processing unit is further operable so as to transfer the command/message data written in the predefined write file from a cache memory to said device interface controller.

21. The system as claimed in claim 19, wherein said protocol-processing unit is further operable so as to disable a cache memory prior to writing of the command/message data thereby in the predefined write file.

22. The system as claimed in claim 19, wherein said device interface controller is further operable so as to determine whether the command/message data is written in the predefined write file,

said device interface controller translating the command/message data into the corresponding command/message and transmitting the corresponding command/message to the I/O device only when it is determined thereby that the command/message data is written in the predefined write file.

23. The system as claimed in claim 19, wherein said protocol-processing unit is operable in one of a filename access mode, where said protocol-processing unit writes the command/message data in the predefined write file with reference to a filename of the predefined write 20 file, and a logical address access mode, where said protocol-processing unit writes the command/message data in the predefined write file with reference to a logical address of the predefined write file.

24. The system as claimed in claim 19, wherein said device interface controller is further operable so as to receive a result from the I/O device, so as to translate the result into response data, and so as to transmit the response data thus translated to said protocol-processing unit.

25. The system as claimed in claim 24, wherein said protocol-processing unit is further operable so as to read the response data from a predefined read file.

26. The system as claimed in claim 25, wherein said device interface controller is further operable so as to determine whether the response data is read from the predefined read file,

said device interface controller translating the result into the response data and transmitting the response data to said protocol-processing unit only when it is determined thereby that the response data is read from the predefined read file.

27. The system as claimed in claim 25, wherein said protocol-processing unit reads data, the size of which is larger than that of a cache memory, thereby permitting said protocol-processing unit to read the response data from said device interface controller and not from the cache memory.

28. The system as claimed in claim 25, wherein said protocol-processing unit reads a plurality of offset sectors of the predefined read file, thereby permitting said protocol-processing unit to read the response data from said device interface controller and not from a cache memory.

29. The system as claimed in claim 28, wherein said protocol-processing unit reads the offset sectors of the predefined read file in one of an incrementing manner and a decrementing manner.

30. The system as claimed in claim 25, wherein said protocol-processing unit reads data in an accumulative manner, thereby permitting said protocol-processing unit to read the response data from said device interface controller and not from a cache memory.

31. The system as claimed in claim 25, wherein said protocol-processing unit is operable in one of a filename access mode, where said protocol-processing unit reads the response data from the predefined read file with reference to a filename of the predefined read file, and a logical address access mode, where said protocol-processing unit reads the response data from the predefined read file with reference to a logical address of the predefined read file.

32. The system as claimed in claim 25, wherein the predefined write and read files are the same file.

33. The system as claimed in claim 25, wherein the predefined write and read files are different files.

34. The system as claimed in claim 25, wherein said device interface controller serves as a virtual memory with a file format architecture, which includes the predefined read and write files, when there is no flash memory connected thereto, and said device interface controller and the I/O device constitute a virtual memory card.

35. The system as claimed in claim 19, further comprising a flash memory coupled to said device interface controller, wherein said device interface controller, the I/O device, and said flash memory constitute a memory card.

36. The system as claimed in claim 19, wherein said device interface controller is connected to said protocol-processing unit via a device interface that complies with a standard established for small form memory card interface.

37. The system as claimed in claim 36, wherein said device interface is one of a secure digital (SD) memory card compliant interface, a multimedia card (MMC) memory card compliant interface, a memory stick (MS) memory card compliant interface, and an MS micro (M2) memory card compliant interface.