Arbitration Based Allocation of a Shared Resource with Reduced Latencies

• US 20100070667A1
• Filed: 09/16/2008
• Published: 03/18/2010
• Est. Priority Date: 09/16/2008
• Status: Active Grant

• Current Assignee: NVIDIA Corporation
• Original Assignee: NVIDIA Corporation
• Inventors: Mittal, Aditya
• Granted Patent: US 8,356,128 B2
• Time in Patent Office: Days
• US Class Current: 710/117
• CPC Class Codes: G06F 13/364 using independent requests or grants, e.g. using separated request and grant lines

Abstract

A digital processing system employing multiple arbiters, all designed to allocate a resource to a same entity in response to a same condition. In an embodiment, the entities needing the resource may send a request to all the arbiters, and the specific entity to which the resource is allocated, receives indication of the allocation from a closest one of the arbiters. As a result, the latency in receipt of indication of allocation may be reduced. The features are described in the context of a bus as a resource.

Claims

1. A digital processing system comprising:

a plurality of entities;

a resource which can be used by only one of said plurality of entities at a given time; and

a plurality of arbiters, each designed individually to allocate said resource to a same entity in response to a same condition.

2. The digital processing system of claim 1, wherein each of said plurality of entities is designed to send a request to all of said plurality of arbiters when the corresponding entity needs said resource, wherein said condition comprises each of said plurality of arbiters receiving said request from a same set of entities contained in said plurality of entities.

3. The digital processing system of claim 2, further comprising:

a plurality of response lines, wherein each entity is coupled to a corresponding closest one of said plurality of arbiters by a corresponding response line,

wherein the connected arbiter indicates allocation of said resource to an entity on the connected response line.

4. The digital processing system of claim 3, further comprising:

a plurality of request lines, each connecting one of said plurality of entities to one or more of said plurality of arbiters,

wherein an entity asserts a corresponding request line to send said request to the arbiters connected to the same request line.

5. The digital processing system of claim 4, further comprising:

a clock generator to generate a clock signal with a sequence of cycles, wherein each of said plurality of entities and said plurality of arbiters are operable based on said clock signal,

wherein each of said plurality of arbiters is designed to allocate said resource to one of said plurality of entities and the allocated entity receives indication of allocation within a single cycle of said clock signal after sending said request.

6. The digital processing system of claim 5, wherein a period of said clock signal is less than or equal to 3 nano seconds.

7. The digital processing system of claim 4, wherein said resource comprises a bus, and said plurality of entities comprise a bridge, a processor and a direct memory access (DMA) controller.

8. The digital processing system of claim 7, wherein said processor is a single central processing unit (CPU) and said plurality of arbiters are implemented external to said single CPU.

9. A digital processing system comprising:

a plurality of components;

a bus operable according to a clock signal having a sequence of clock cycles, wherein a single component can send data values on said bus in any one clock cycle; and

a plurality of arbiters, each to determine a specific component to which to allocate said bus in a clock cycle contained in said sequence of clock cycles.

10. The digital processing system of claim 9, wherein each of said arbiters is designed to receive a corresponding request from all of said plurality of components which require to use said bus in said clock cycle, and all of said arbiters are designed to determine the same component to allocate said bus when a same set of components request said bus, wherein said condition comprises each of said plurality of arbiters receiving said request from said same set of components.

11. The digital processing system of claim 10, further comprising:

a central processing unit (CPU) connected to said bus;

a second bus operating at a lower speed compared to said bus;

a peripheral interface connected to said second bus; and

a bridge connecting said bus with said second bus,

wherein each of said CPU and said bridge is a corresponding one of said plurality of components.

12. The digital processing system of claim 11, wherein said plurality of components further comprise a graphics controller connected to said bus.

13. The digital processing system of claim 12, wherein a period of said clock signal is less than or equal to 3 nano seconds.

14. A method of allocating a resource among a plurality of entities in a digital processing system, said method comprising:

implementing a plurality of arbiters in said digital processing system, wherein each of said plurality of arbiters is designed individually to allocate said resource to a same entity in response to receipt of a request for said resource from a same group of entities;

receiving in each of said plurality of arbiters a corresponding request for said resource from each of a set of entities requesting said resource, wherein said set of entities is comprised in said plurality of entities;

determining a first entity among said set of entities in all of said plurality of arbiters; and

indicating allocation of said resource to said first entity in response to said determining.

15. The method of claim 14, wherein said indicating is performed only by one of said plurality of arbiters.

16. The method of claim 15, wherein said one of said plurality of arbiters is the closest arbiter to said first entity.

17. The method of claim 14, wherein said resource comprises a bus.

18. The method of claim 17, further comprising:

operating each of said entities using a clock signal having a clock period,

wherein each entity is designed to receive allocation indication within said clock period of asserting a communication path to indicate said request for said resource.

19. The method of claim 19, wherein said clock period is less than or equal to 3 nano seconds.