METHOD TO MONITOR READ/WRITE STATUS OF FLASH MEMORY DEVICES

• US 20100070683A1
• Filed: 09/16/2008
• Published: 03/18/2010
• Est. Priority Date: 09/16/2008
• Status: Active Grant

• Current Assignee: SK Hynix Inc.
• Original Assignee: International Business Machines Corporation
• Inventors: Kelley, Edward E., Delia, Wayne M.
• Granted Patent: US 8,447,913 B2
• Time in Patent Office: Days
• US Class Current: 711/103
• CPC Class Codes: G06F 12/0246 in block erasable memory, e.g. flash memory
• CPC Class Codes: G06F 2212/1032 Reliability improvement, data loss prevention, degraded operation etc
• CPC Class Codes: G06F 2212/7207 management of metadata or control data
• CPC Class Codes: G06F 2212/7209 Validity control, e.g. using flags, time stamps or sequence numbers

Abstract

A method and flash memory device employing the method includes a flash memory device having a logic routine saved on the flash memory being a computer readable medium. The flash memory device generates a plurality of memory inputs and outputs. The logic routine determines a memory input and/or memory output operation, and incrementally counts memory inputs and memory outputs using a counter function of the logic routine. The logic routine determines the total number of the plurality of memory inputs and outputs using the counter function. Additionally, the logic routine generates an alert signal when the total number of the memory inputs and outputs exceeds a predetermined value programmed in the logic routine.

Claims

1. A method for monitoring an electronic memory device, comprising:

providing a flash memory device having a logic routine saved on flash memory being a computer readable medium, the flash memory device communicatable with a processor;

operating the flash memory device generating a plurality of memory inputs and outputs using the processor;

determining a memory input or memory output operation using the logic routine;

incrementally counting a plurality of memory inputs and memory outputs using a counter function of the logic routine;

determining a total number of the plurality of memory inputs and outputs using the counter function of the logic routine; and

generating an alert signal using the logic routine when the total number of the memory inputs and outputs exceeds a predetermined value programmed in the logic routine.

2. The method of claim 1, wherein the predetermined value is a threshold number of memory inputs and outputs being an expected mean time to failure of the flash memory device.

3. The method of claim 2, wherein the logic routine includes a warning function programmable by a user for indicating a specified number of memory input and output operations in relation to the total number of the memory inputs and outputs.

4. The method of claim 3, wherein the warning function includes a plurality of warning signals each indicating a specified number of memory input and output operations in relation to the total number of the memory inputs and outputs.

5. The method of claim 3, further including:

providing a computer system having a computer readable medium having a program stored thereon and the program being executable by the processor, and the logic routine communicating with the processor of the computer system;

sending the alert signal to the processor using the logic routine;

initiating a warning signal using the logic routine when the warning function indicates the predetermined number of memory input and output operations in relation to the total number of the memory inputs and outputs is reached;

receiving the alert signal and the warning signal using the processor; and

initiating a communications signal using the processor to a user for communicating the alert signal and the warning signal.

6. The method of claim 5, wherein the warning signal indicates a life expectancy of the flash memory device.

7. The method of claim 1, wherein the input and output operations include read and write operations.

8. The method of claim 1, wherein a user selectively sets a criteria using a computer system for a warning function of the logic routine for indicating a specified number of memory input and output operations in relation to the total number of the memory inputs and outputs.

9. The method of claim 8, wherein the user selectively sets different criteria for each of a plurality of warnings generated by the warning function of the logic routine.

10. A flash memory device, comprising:

a logic routine saved on flash memory being a computer readable medium, the flash memory communicatable with a computer system having a computer readable medium having a program stored thereon and the program being executable by a processor, the flash memory capable of generating a plurality of memory inputs and outputs; and

the logic routine determining memory input and memory output operations, and the logic routine incrementally counting memory inputs and memory outputs using a counter function of the logic routine, the logic routine determining the total number of the plurality of memory inputs and outputs using the counter function, and the logic routine generating and sending an alert signal to the processor for initiating a warning signal when the total number of the memory inputs and outputs exceeds a predetermined value programmed in the logic routine.

11. The device of claim 10, wherein the predetermined value is a threshold number of memory inputs and outputs being an expected mean time to failure of the flash memory device.

12. The device of claim 10, wherein the program includes a warning function programmable by a user for indicating a predetermined number of memory input and output operations in relation to the total number of the memory inputs and outputs.

13. The device of claim 12, wherein the warning function includes a plurality of warning signals each indicating a specified number of memory input and output operations in relation to the total number of the memory inputs and outputs.

14. The device of claim 10, wherein the input and output operations include read and write operations.

15. The device of claim 10, wherein a user selectively sets a criteria using a computer system for a warning function of the logic routine for indicating a specified number of memory input and output operations in relation to the total number of the memory inputs and outputs.

16. The device of claim 10, wherein the user selectively sets different criteria for each of a plurality of warnings generated by the warning function of the logic routine.

17. A computer program product comprising flash memory as a computer readable medium having recorded thereon a computer program for enabling a processor in a computer system for monitoring the status of memory input and output operations of the flash memory and communicating with the computer system, the flash memory operating to generate a plurality of memory inputs and outputs on the flash memory, the program executing steps comprising:

determining a memory input and memory output operation using the program;

incrementally counting memory inputs and memory outputs using a counter function of the program;

determining a total number of the plurality of memory inputs and outputs using the counter function of the program; and

generating an alert signal using the program when the total number of the memory inputs and outputs exceeds a predetermined value programmed in the program.

18. The computer program product of claim 17, further comprising:

initiating a warning signal using the logic routine when the warning function indicates the predetermined number of memory input and output operations in relation to the total number of the memory inputs and outputs is reached;

receiving the alert signal and the warning signal using the processor; and

initiating a communications signal using the processor to a user for communicating the alert signal and the warning signal.