METHOD AND APPARATUS FOR ENCODING AND DECODING DATA

• US 20100070822A1
• Filed: 09/11/2009
• Published: 03/18/2010
• Est. Priority Date: 03/12/2007
• Status: Abandoned Application

• Current Assignee: Huawei Technologies Co., Ltd. (Huawei Investment & Holding Co., Ltd.)
• Original Assignee: Huawei Technologies Co., Ltd. (Huawei Investment & Holding Co., Ltd.)
• Inventors: Feng, Dongning, Leung, Raymond W.K., Geng, Dongyu
• Application Number:
  US12/557,714
• Publication Number:
  US 20100070822A1
• Time in Patent Office: Days
• US Class Current: 714/752
• CPC Class Codes: H04L 1/007 Unequal error protection for format H04L1/0078; for codes per se H03M13/35
• CPC Class Codes: H04L 1/0072 Error control for data other than payload data, e.g. control data

Abstract

The present invention relates to the communication field, and discloses a method and an apparatus for encoding, decoding, receiving and transmitting data to improve the encoding gain of the FEC encoding without increasing transmission overhead. In the present invention, no FEC encoding is performed for the minor bits in the block header of the information blocks. The block header may be a sync header. The bit indicative of the data type serves as a major bit, and is protected through FEC encoding; the bit for the only purpose of block synchronization serves as a minor bit, which is not involved in the FEC encoding and decoding. When the buffered data are deficient, padding blocks are padded into the buffer to trigger the FEC encoding in time; after the FEC encoding, the padding block is removed from the encoding result, thus avoiding transmission of unnecessary data.

Claims

1. A method for encoding and transmitting data, comprising:

performing Forward Error Correction, FEC, encoding on the information data and M major bits in the block header of information blocks;

generating check blocks by FEC encoding; and

sending the information blocks and the check blocks;

wherein each information block comprises a block header and information data, and the block header comprises M major bits and N minor bits, M≧

0, N≧

1.

2. The method for encoding and transmitting data according to claim 1, wherein the block header is a sync header comprising a major bit and a minor bit, the major bit of sync header used for block synchronization and indicating the type of the information data of the block, and the minor bit of sync header used for block synchronization, and before performing FEC encoding, the method further comprises:

performing line encoding on the information data, and

generating the major bit and the minor bit in the sync header.

3. The method for encoding and transmitting data according to claim 1, wherein the block header is a sync header comprising a major bit and a minor bit, the major bit of sync header used for block synchronization and indicating the type of the information data of the block, and the minor bit of sync header used for block synchronization, and before performing FEC encoding, the method further comprises:

performing line encoding on the information data;

generating the major bit in the sync header;

negating the major bit to obtain the minor bit in the sync header.

4. The method for encoding and transmitting data according to claim 1, before performing FEC encoding, the method further comprising:

scrambling the information data.

5. The method for encoding and transmitting data according to claim 1, if the total length of the information data and the major bits is shorter than the length required for FEC encoding, the method further comprising:

adding predetermined padding bits to the sequence comprising the information data and the major bits before performing FEC encoding, wherein the total length of the information data, the major bits and the added predetermined padding bits is equal to the length required for the FEC encoding, and the information data, the major bits and the added predetermined padding bits are used for the FEC encoding to generate the check blocks; and

after performing FEC encoding, removing the added predetermined padding bits from FEC encoding result.

6. A method for receiving and decoding data, comprising:

receiving information blocks and check blocks;

performing Forward Error Correction, FEC, decoding on the information data and M major bits in the block header of the received information block with the check blocks;

wherein each information block comprises a block header and information data, and the block header comprises M major bits and N minor bits, M≧

0, N≧

1.

7. The method for receiving and decoding data according to claim 6, wherein the block header is a sync header comprising a major bit and a minor bit, the major bit of sync header used for block synchronization and indicating the type of the information data of the block, and the minor bit of sync header used for block synchronization, and after performing FEC decoding, the method further comprises:

performing line decoding on information block comprising the minor bit, the information data and the major bit after FEC decoding;

wherein the type of the information data is determined according to the major bit during line decoding and the minor bit involved in line decoding is obtained by receiving or by negating the major bit obtained by FEC decoding.

8. The method for receiving and decoding data according to claim 6, wherein the block header is a sync header comprising a major bit and a minor bit, the major bit of sync header used for block synchronization and indicating the type of the information data of the block, and the minor bit of sync header used for block synchronization, and after performing FEC decoding, the method further comprises:

performing line decoding on the information data and the major bit after FEC decoding;

wherein the type of the information data is determined according to the major bit during line decoding.

9. The method for receiving and decoding data according to claim 6, after performing FEC decoding, the method further comprising:

descrambling the information data.

10. The method for receiving and decoding data according to claim 6, if the total length of the information data and the major bits is shorter than the length required for FEC decoding, the method further comprising:

adding predetermined padding bits to the sequence comprising the information data and the major bits before performing FEC decoding, wherein the total length of the information data, the major bits and the added predetermined padding bits is equal to the length required for the FEC decoding, and the information data, the major bits and the added predetermined padding bits are used for the FEC decoding with the check blocks; and

after performing FEC decoding, removing the added predetermined padding bits from FEC decoding result.

11. An apparatus for encoding and transmitting data, comprising:

a Forward Error Correction, FEC, encoding module, configured to perform FEC encoding on the information data and M major bits in the block header of information blocks, and generate check blocks by FEC encoding; and

a sending module, configured to send the information blocks and the check blocks;

wherein each information block comprises a block header and information data, and the block header comprises M major bits and N minor bits, M≧

0, N≧

1.

12. The apparatus for encoding and transmitting data according to claim 11, wherein the block header is a sync header comprising a major bit and a minor bit, the major bit of sync header used for block synchronization and indicating the type of the information data of the block, and the minor bit of sync header used for block synchronization, and the apparatus further comprises:

a first line encoding module, configured to perform line encoding on the information data to generate the major bit and the minor bit in the sync header, output the information data and the major bit to the FEC encoding module, and output the minor bit with the result of the FEC encoding module to the sending module.

13. The apparatus for encoding and transmitting data according to claim 11, wherein the block header is a sync header comprising a major bit and a minor bit, the major bit of sync header used for block synchronization and indicating the type of the information data of the block, and the minor bit of sync header used for block synchronization, and the apparatus further comprises:

a second line encoding module, configured to perform line encoding on the information data to generate the major bit, and output the information data and the major bit to the FEC encoding module;

a negating module, configured to negate the major bits output by the second line encoding module, and output the negating result with the processing result of the FEC encoding module to the sending module.

14. The apparatus for encoding and transmitting data according to claim 11, the apparatus further comprising:

a scrambling module, configured to scramble the information data;

wherein the scrambling result is output to the first line encoding module or the second line encoding module, or the scrambling module scrambles the information data output by the first line encoding module or the second line encoding module and then outputs the scrambling result to the FEC encoding module.

15. The apparatus for encoding and transmitting data according to claim 11, if the total length of the information data and the major bits is shorter than the length required for FEC encoding, the apparatus further comprising:

a padding module, configured to buffer the sequence comprising the information data and the major bits, and insert predetermined padding bits in a predetermined position of the sequence, and then output the information data, the major bits and the inserted predetermined padding bits to the FEC encoding module, wherein the total length of the information data, the major bits and the inserted predetermined padding bits is equal to the length required for the FEC encoding;

a filter, configured to remove the inserted predetermined padding bits from the encoding result output by the FEC encoding module, and then output to the sending module.

16. An apparatus for receiving and decoding data, comprising:

a receiving module, configured to receive information blocks and check blocks; and

a Forward Error Correction, FEC, decoding module, configured to perform FEC decoding on the information data and M major bits in the block header of the received information block with the check blocks;

wherein each information block comprises a block header and information data, and the block header comprises M major bits and N minor bits, M≧

0, N≧

1.

17. The apparatus for receiving and decoding data according to claim 16, wherein the block header is a sync header comprising a major bit and a minor bit, the major bit of sync header used for block synchronization and indicating the type of the information data of the block, and the minor bit of sync header used for block synchronization, and the apparatus further comprises:

a first line decoding module, configured to perform line decoding on the information blocks comprising the minor bit, the information data and the major bit after FEC decoding, wherein the type of the information data is determined according to the major bit during line decoding and the minor bit involved in line decoding is output by the receiving module or obtained by negating the major bit of the information blocks output by the FEC decoding module.

18. The apparatus for receiving and decoding data according to claim 16, wherein the block header is a sync header comprising a major bit and a minor bit, the major bit of sync header used for block synchronization and indicating the type of the information data of the block, and the minor bit of sync header used for block synchronization, and the apparatus further comprises:

a second line decoding module, configured to perform line decoding on the information data and the major bit of the information blocks after FEC decoding, wherein the type of the information data is determined according to the major bit during line decoding.

19. The apparatus for receiving and decoding data according to claim 16, the apparatus further comprising:

a descrambling module, configured to descramble the information data;

wherein the descrambling module descrambles the information data output by the first line decoding module or the second line decoding module, or the descrambling module descrambles the information data output by the FEC decoding module and then outputs the descrambling result to the first line decoding module or the second line decoding module.

20. The apparatus for receiving and decoding data according to claim 16, if the total length of the information data and the major bits is shorter than the length required for FEC decoding, the apparatus further comprising:

a padding module, configured to buffer the sequence comprising the information data and the major bits, and insert predetermined padding bits in a predetermined position of the sequence, and then output the information data, the major bits and the inserted predetermined padding bits to the FEC decoding module, wherein the total length of the information data, the major bits and the added predetermined padding bits is equal to the length required for the FEC decoding; and

a filter, configured to remove the inserted predetermined padding bits from the decoding result output by the FEC decoding module.