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DISPLAY DEVICE

  • US 20100072470A1
  • Filed: 09/10/2009
  • Published: 03/25/2010
  • Est. Priority Date: 09/19/2008
  • Status: Active Grant
First Claim
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1. A display device comprising:

  • a plurality of scan lines and a plurality of signal lines which intersect with each other over a substrate;

    a pixel portion over the substrate, the pixel portion including a plurality of pixel electrodes arranged in matrix;

    a signal input terminal in a periphery of the substrate; and

    a non-linear element between the pixel portion and the signal input terminal,wherein the pixel portion includes a thin film transistor,wherein the thin film transistor includes;

    a first oxide semiconductor layer including a channel formation region;

    a gate electrode connected to one of the plurality of scan lines;

    a first wiring layer connecting the one of the plurality of signal lines and the first oxide semiconductor layer; and

    a second wiring layer connecting one of the plurality of pixel electrodes and the first oxide semiconductor layer, andwherein the non-linear element includes;

    a gate electrode connected to one of the plurality of scan lines or one of the plurality of signal lines;

    a gate insulating layer covering the gate electrode;

    a second oxide semiconductor layer over the gate insulating layer, the second oxide semiconductor layer overlapping with the gate electrode;

    a channel protective layer over the second oxide semiconductor layer, the channel protective layer overlapping with a channel formation region of the second oxide semiconductor layer;

    a third wiring layer over the channel protective layer and the second oxide semiconductor layer, wherein an end portion of the third wiring layer overlaps with the gate electrode, and wherein the third wiring layer includes a stack of a first conductive layer and a third oxide semiconductor layer;

    a fourth wiring layer over the channel protective layer and the second oxide semiconductor layer, wherein an end portion of the fourth wiring layer overlaps with the gate electrode, and wherein the fourth wiring layer includes a stack of a second conductive layer and a fourth oxide semiconductor layer; and

    a fifth wiring layer connecting the gate electrode and one of the third wiring layer and the fourth wiring layer.

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