Thin film transistor and method of manufacturing the same

• US 20100072480A1
• Filed: 05/06/2009
• Published: 03/25/2010
• Est. Priority Date: 09/24/2008
• Status: Active Grant

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Samsung Electronics Co. Ltd.
• Inventors: Son, Kyung-seok, Ryu, Myung-kwan, Lee, Sang-yoon, Jung, Ji-sim, Kim, Tae-sang, Park, Kyung-bae, Kwon, Jang-yeon, Yoo, Byung-wook
• Granted Patent: US 8,263,978 B2
• Time in Patent Office: Days
• US Class Current: 257/66
• CPC Class Codes: H01L 21/02532 Silicon, silicon germanium, germanium
• CPC Class Codes: H01L 21/02672 using crystallisation enhancing elements
• CPC Class Codes: H01L 27/1277 using a crystallisation promoting species, e.g. local introduction of Ni catalyst
• CPC Class Codes: H01L 29/66765 Lateral single gate single channel transistors with inverted structure, i.e. the channel layer is formed after the gate
• CPC Class Codes: H01L 29/78696 characterised by the structure of the channel, e.g. multichannel, transverse or longitudinal shape, length or width, doping structure, or the overlap or alignment between the channel and the gate, the source or the drain, or the contacting structure of the channel H01L29/78612 takes precedence; transistors having a drain offset region or a lightly doped drain [LDD] H01L29/78621

Abstract

A thin film transistor (TFT) and a method of manufacturing the same are provided, the TFT including a gate insulating layer on a gate. A channel may be formed on a portion of the gate insulating layer corresponding to the gate. A metal material may be formed on a surface of the channel. The metal material crystallizes the channel. A source and a drain may contact side surfaces of the channel.

Claims

1. A thin film transistor (TFT), comprising:

a gate insulating layer on a gate;

a crystallized channel on a portion of the gate insulating layer corresponding to the gate;

a metal material on a surface of the channel, wherein the metal material crystallizes the channel; and

a source and a drain contacting side surfaces of the channel.

2. The TFT of claim 1, wherein the metal material is on the surface of the channel between the channel and the source and between the channel and the drain.

3. The TFT of claim 1, wherein the metal material is on a portion of the channel wherein the channel and the source overlap and on a portion of the channel wherein the channel and the drain overlap.

4. The TFT of claim 1, wherein the channel is over the gate.

5. The TFT of claim 1, wherein the metal material has a thickness of about 0.1-nm to 20-nm.

6. The TFT of claim 1, wherein the channel is formed of polysilicon.

7. The TFT of claim 1, further comprising an intermediate layer between the channel and the source and between the channel and the drain, wherein the intermediate layer reduces contact resistance between the channel and the source and between the channel and the drain.

8. The TFT of claim 7, wherein the metal material includes at least one selected from the group consisting of nickel (Ni), silver (Ag), gold (Au), palladium (Pd), cobalt (Co), copper (Cu), iron (Fe), aluminum (Al), chromium (Cr), platinum (Pt) and combinations thereof.

9. A method of manufacturing an oxide TFT, comprising:

forming a gate on a substrate;

forming a gate insulating layer on the substrate and the gate;

depositing a metal material on the gate insulating layer;

coating a channel material on the metal material;

annealing the coated metal material such that a channel is formed;

coating a conductive material on the channel; and

etching the coated conductive material until a surface of the channel is exposed.

10. The method of claim 9, wherein the channel material is amorphous silicon.

11. The method of claim 9, further comprising forming an intermediate layer between the channel and a source and between the channel and a drain, wherein the intermediate layer reduces contact resistance between the channel and the source and between the channel and the drain.

12. The method of claim 9, wherein the metal material includes at least one selected from the group consisting of nickel (Ni), silver (Ag), gold (Au), palladium (Pd), cobalt (Co), copper (Cu), iron (Fe), aluminum (Al), chromium (Cr), platinum (Pt) and combinations thereof.

13. The method of claim 9, wherein the metal material has a thickness of about 0.1-nm to 20-nm.

14. The method of claim 9, wherein the channel is formed over the gate.

15. The method of claim 9, further comprising forming a source and a drain from the etched conductive material.

16. The method of claim 15, wherein the metal material diffuses to a surface of the channel during annealing of the coated metal material.

17. The method of claim 16, further comprising removing the surface of the channel between the source and the drain.

18. A method of manufacturing an oxide TFT, comprising:

forming a gate on a substrate;

forming a gate insulating layer on the substrate and the gate;

depositing a metal material on the gate insulating layer;

coating a channel material on the metal material;

forming a channel from the channel material, wherein the metal material diffuses to an upper surface of the channel;

coating a conductive material on the channel; and

etching the coated conductive material until the upper surface of the channel is exposed.

19. The method of claim 18, wherein the metal material crystallizes the channel.

20. The method of claim 18, forming the channel includes annealing the channel material.