Silicon break over diode

• US 20100072512A1
• Filed: 09/23/2008
• Published: 03/25/2010
• Est. Priority Date: 09/23/2008
• Status: Active Grant

• Current Assignee: General Atomics, Inc.
• Original Assignee: Optiswitch Technology Corporation
• Inventors: Giorgi, David M., Navapanich, Tajchai
• Granted Patent: US 7,868,352 B2
• Time in Patent Office: Days
• US Class Current: 257/109
• CPC Class Codes: H01L 29/87 Thyristor diodes, e.g. Shockley diodes, break-over diodes

Abstract

A Break Over Diode (“BOD”) device is a gate-less two terminal high power semiconductor switch in which transitions from a blocking state to a conducting state are triggered by a dV/dt pulse to the anode. The BOD device can be thought of as two cross-coupled PNP and NPN transistors, and includes both anode and cathode shorts which reduce the gain of the NPN and PNP transistors by shunting some current away from their bases directly to their emitters, thereby improving blocking. Moreover, the anode and cathode shorts in conjunction with the device blocking junction form PN diodes which are distributed throughout the bulk of the material and function as anti-parallel diodes to the base-emitter junctions of the PNP and NPN transistors, which enables the BOD device to handle a larger current reversal for a longer period of time. The P base layer may be made thin to decrease the voltage fall time from full blocking to full conduction, and the cathode and anode shorts may be provided in a honeycomb pattern.

Claims

1. A two-terminal semiconductor switching device comprising:

a P+ layer of semiconductor material having essentially parallel first and second major surfaces;

a plurality of N+ regions distributed in the P+ layer and passing through the P+ layer between the first and second major surfaces thereof;

a metallization layer disposed on the first surface of the P+ layer and on a surface portion of each of the N+ regions;

a N−

layer of semiconductor material having essentially parallel first and second major surfaces, the first major surface of the N−

layer being disposed proximate the second major surface of the P+ layer;

a P layer of semiconductor material having essentially parallel first and second major surfaces, the first major surface of the P layer being disposed contiguous to the second major surface of the N−

layer to form a blocking junction;

a N+ layer of semiconductor material having essentially parallel first and second major surfaces, the first major surface of the N+ layer being disposed proximate the second major surface of the P layer;

a plurality of P+ regions distributed in the N+ layer and passing through the N+ layer between the first and second major surfaces thereof; and

a metallization layer disposed on the second surface of the N+ layer and on a surface portion of each of the P+ regions.

2. The semiconductor switching device of claim 1 wherein:

the N+ regions are distributed uniformly in the P+ layer in a hexagonal arrangement about centrally disposed members;

the P+ regions are distributed uniformly in the N+ layer in a hexagonal arrangement about centrally disposed members; and

the P+ regions and the N+ regions are aligned with one another.

3. The semiconductor switching device of claim 1 wherein the P layer of semiconductor material is made thin for improving device switching speed from full blocking to full conduction.

4. The semiconductor switching device of claim 1 further comprising a N layer of semiconductor material disposed between the P+ layer and the N−

layer for providing a field stop.

5. The semiconductor switching device of claim 1 wherein:

the P layer of semiconductor material is made thin for improving device switching speed from full blocking to full conduction;

the N+ regions are distributed uniformly in the P+ layer in a hexagonal arrangement about centrally disposed members;

the P+ regions are distributed uniformly in the N+ layer in a hexagonal arrangement about centrally disposed members; and

the P+ regions and the N+ regions are aligned with one another.