METAL GATE STRESS FILM FOR MOBILITY ENHANCEMENT IN FinFET DEVICE

• US 20100072553A1
• Filed: 09/23/2008
• Published: 03/25/2010
• Est. Priority Date: 09/23/2008
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Yeh, Chih Chieh, Wann, Clement H., XU, Jeff J., Chang, Chih-Sheng
• Granted Patent: US 7,915,112 B2
• Time in Patent Office: Days
• US Class Current: 257/369
• CPC Class Codes: H01L 21/823807 with a particular manufacturing method of the channel structures, e.g. channel implants, halo or pocket implants, or channel materials
• CPC Class Codes: H01L 21/823821 with a particular manufacturing method of transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 21/823828 with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes
• CPC Class Codes: H01L 21/845 including field-effect transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/66545 using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate
• CPC Class Codes: H01L 29/66795 with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/785 having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET

Abstract

A CMOS FinFET semiconductor device provides an NMOS FinFET device that includes a compressive stress metal gate layer over semiconductor fins and a PMOS FinFET device that includes a tensile stress metal gate layer over semiconductor fins. A process for forming the same includes a selective annealing process that selectively converts a compressive metal gate film formed over the PMOS device to the tensile stress metal gate film.

Claims

1. A method for forming a CMOS FinFET device comprising:

forming a plurality of NMOS and PMOS regions on a substrate;

forming a compressive PVD (physical vapor deposition) metal layer over said NMOS and PMOS regions;

selectively converting said compressive PVD metal layer formed in said PMOS region, to a tensile metal layer; and

forming gate electrodes overlying said compressive PVD metal layer in said NMOS region and overlying said tensile metal layer in said PMOS region.

2. The method as in claim 1, wherein:

said forming a plurality of NMOS and PMOS regions comprises forming a plurality of semiconductor fins in each of said NMOS and PMOS regions on said substrate;

said forming a compressive PVD metal layer comprises forming said compressive PVD metal layer over said semiconductor fins in each of said NMOS and PMOS regions; and

said forming gate electrodes comprises forming said gate electrodes over said semiconductor fins including over said compressive PVD metal layer in said NMOS region and over said tensile metal layer in said PMOS region.

3. The method as in claim 2, wherein said forming a compressive PVD metal layer comprises forming a TiN layer over said semiconductor fins in each of said NMOS and PMOS regions.

4. The method as in claim 2, wherein said semiconductor fins are formed of silicon or SiGe.

5. The method as in claim 2, wherein said selectively converting comprises said tensile metal layer having a tensile stress of greater than about 4 GPa.

6. The method as in claim 2 further comprising forming a high-k gate dielectric over said semiconductor fins in each of said NMOS and PMOS regions, and wherein said compressive PVD metal layer is disposed over said high-k gate dielectric in each of said NMOS and PMOS regions.

7. The method as in claim 2, wherein said forming a compressive PVD metal layer comprises separately forming a first compressive PVD metal layer over said semiconductor fins in said PMOS region and a second compressive PVD metal layer over said semiconductor fins in said NMOS region, and wherein said selectively converting comprises performing a spike or laser anneal when said first compressive PVD metal layer is disposed over said semiconductor fins in said PMOS region and when said second compressive PVD metal layer is not present in said NMOS region.

8. The method as in claim 7, wherein said forming a first compressive PVD metal layer over said semiconductor fins in said NMOS region and forming a second compressive PVD metal layer over said semiconductor fins in said PMOS region and said selectively converting comprise:

forming-dummy gates over a sacrificial film over said semiconductor fins in each of said NMOS and PMOS regions;

performing a source/drain implant and a further anneal in at least one of said NMOS and PMOS regions;

depositing a dielectric over said semiconductor fins and said dummy gates in each of said NMOS and PMOS regions;

planarizing said dielectric to expose respective surfaces of said dummy gates in each of said NMOS and PMOS regions;

selectively removing said dummy gate from said PMOS region;

depositing a high-k gate dielectric on said semiconductor fins in said PMOS region;

depositing said first compressive PVD metal layer;

performing said spike or laser anneal thereby selectively converting said first compressive PVD metal layer to said tensile metal film;

removing said dummy gate from said NMOS region;

depositing a further high-k dielectric material on said semiconductor fins in said NMOS region;

depositing said second compressive PVD metal layer; and

forming polysilicon or metal gates over said tensile metal film and said semiconductor fins in said PMOS region and over said second compressive PVD metal layer in said NMOS region, said second compressive PVD metal layer retaining compressive characteristics.

9. The method as in claim 2, wherein said plurality of semiconductor fins have a pitch no greater than about 25 nm and said compressive PVD metal layer comprises TiN having a thickness of about 3-5 nm.

10. The method as in claim 1, wherein said selectively converting comprises spike annealing at a temperature within the range of about 1000°

C. to about 1100°

C.

11. A method for forming a CMOS FinFET device comprising:

forming semiconductor fins in NMOS and PMOS regions over a substrate;

forming dummy gates overlying a sacrificial film overlying said semiconductor fins in each of said NMOS and PMOS regions;

performing a source/drain implant in at least one of said NMOS and PMOS regions;

depositing a dielectric over said semiconductor fins and said dummy gates;

planarizing said dielectric to expose surfaces of said dummy gates in each of said NMOS and PMOS regions;

selectively removing said dummy gates from said PMOS region;

depositing a high-k gate dielectric on said semiconductor fins in said PMOS region;

using physical vapor deposition techniques to deposit a first compressive metal film on said fins in said PMOS region;

heating thereby converting said first compressive metal film to a tensile metal film; and

forming functional gates over said semiconductor fins in said PMOS region.

12. The method as in claim 11, further comprising, after said forming functional gates in said PMOS region,

removing said dummy gates from over said NMOS region;

depositing a further high-k dielectric material on said semiconductor fins in said NMOS region;

depositing a second compressive metal film using physical vapor deposition techniques on said semiconductor fins in said NMOS region; and

forming functional gates over said compressive metal film and said fins in said NMOS region with said second compressive metal film retaining compressive characteristics, and

wherein said functional gates in said PMOS region and said functional gates in said NMOS region each comprise polysilicon or metal gates.

13. The method as in claim 12, wherein each of said first compressive metal film and said second compressive metal film comprises TiN, and said heating comprises a spike or laser anneal at a temperature within the range of about 1000°

C. to 1300°

C. and whereby said converting produces said tensile metal film having a stress of about 4 GPa or greater.

14. The method as in claim 12, wherein each of said selectively removing said dummy gates from said PMOS region and said removing said dummy gates from over said NMOS region comprise etching and stopping at said sacrificial film.

15. The method as in claim 11, wherein said semiconductor fins are formed of silicon, SiGe, Ge or group III-IV compound semiconductors.

16. A CMOS FinFET device comprising:

an NMOS portion having semiconductor fins and an NMOS gate disposed over and alongside said semiconductor fins and a first high-k dielectric and a compressive metal film disposed between said semiconductor fins and said NMOS gate; and

a PMOS portion having semiconductor fins and a PMOS gate disposed over and alongside said semiconductor fins and a second high-k dielectric and a tensile metal film disposed between said semiconductor fins and said PMOS gate.

17. The CMOS FinFET device as in claim 16, wherein said compressive metal film and said tensile metal film each comprise TiN.

18. The CMOS FinFET device as in claim 17, wherein said TiN is a layer that has a thickness between about 3-5 nm.

19. The CMOS FinFET device as in claim 16, wherein said semiconductor fins have a pitch of about 35 nm or less.

20. The CMOS FinFET device as in claim 16, wherein said compressive metal film has a stress of at least 4 GPa.