WAFER BONDING METHOD AND WAFER STACK FORMED THEREBY

• US 20100072555A1
• Filed: 09/23/2009
• Published: 03/25/2010
• Est. Priority Date: 09/24/2008
• Status: Active Grant

• Current Assignee: IP3 2017, Series 200 of Allied Security Trust I (Allied Security Trust)
• Original Assignee: Evigia Systems, Inc.
• Inventors: Meng, Guangqing, Yazdi, Navid, Zhang, Yafan
• Granted Patent: US 8,119,498 B2
• Time in Patent Office: Days
• US Class Current: 257/369
• CPC Class Codes: H01L 21/187 by direct bonding
• CPC Class Codes: H01L 25/50 Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00 H01L21/50 takes precedence
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

A wafer bonding process that compensates for curvatures in wafer surfaces, and a wafer stack produced by the bonding process. The process entails forming a groove in a surface of a first wafer, depositing a bonding stack on a surface of a second wafer, aligning and mating the first and second wafers so that the bonding stack on the second wafer contacts a bonding site on the first wafer, and then heating the first and second wafers to reflow the bonding stack. The groove either surrounds the bonding site or lies entirely within the bonding site, and the heating step forms a molten bonding material, causes at least a portion of the molten bonding material to flow into the groove, and forms a bonding structure that bonds the second wafer to the first wafer. Bonding stacks having different lateral surface areas can be deposited to form bonding structures of different heights to compensate for variations in the wafer gap.

Claims

1. A wafer bonding process comprising:

providing a first bonding site on a surface of a first wafer;

depositing at least a first bonding stack on a surface of a second wafer;

forming at least a first groove in the surface of the first wafer, the first groove either surrounding the first bonding site or lying entirely within the first bonding site;

aligning and mating the first and second wafers so that the first bonding stack on the second wafer contacts the first bonding site on the first wafer; and

then

heating the first and second wafers to reflow the first bonding stack on the second wafer, form a molten bonding material, cause at least a portion of the molten bonding material to flow into the first groove in the surface of the first wafer, and form a first bonding structure that bonds to the first bonding site of the first wafer and bonds the second wafer to the first wafer.

2. The process according to claim 1, wherein the first groove surrounds and does not lie within the first bonding site, does not contact the first bonding stack after the first and second wafers are aligned and mated, and is a barrier to overflow of the molten bonding material away from the first bonding site during the heating step.

3. The process according to claim 2, wherein the first groove is a continuous ring that surrounds the first bonding site.

4. The process according to claim 2, wherein the first groove is a segment of a first discontinuous ring that surrounds the first bonding site.

5. The process according to claim 4, further comprising forming a second discontinuous ring that surrounds the first bonding site and surrounds the first discontinuous ring.

6. The process according to claim 5, wherein at least one of the first and second discontinuous rings defines a gap that is overlapped by the other of the first and second discontinuous rings.

7. The process according to claim 2, further comprising depositing at least a second bonding stack on the surface of the second wafer, the second bonding stack defining a continuous ring that surrounds the first groove in the surface of the first wafer, wherein the aligning and mating step comprises aligning, mating and contacting the second bonding stack on the second wafer with a second bonding site on the first wafer, and the heating step comprises reflowing the second bonding stack on the second wafer, forming a second molten bonding material, and causing at least a portion of the second molten bonding material to flow into the first groove in the surface of the first wafer.

8. The process according to claim 2, further comprising forming a second groove that lies entirely within the first bonding site, contacts the first bonding stack after the first and second wafers are aligned and mated, and draws the molten bonding material therein by capillary flow during the heating step.

9. The process according to claim 1, wherein the first groove lies entirely within the first bonding site, contacts the first bonding stack after the first and second wafers are aligned and mated, and draws the molten bonding material therein by capillary flow during the heating step.

10. The process according to claim 1, wherein at least one of the surfaces of the first and second wafers has a radius of curvature of less than one hundred meters, and the first and second wafers define an interface therebetween and a gap between the surfaces of the first and second wafers that has a width that is greater at a first location of the interface than at a second location of the interface.

11. The process according to claim 10, further comprising depositing at least a second bonding stack on the surface of the second wafer, wherein the first bonding stack is located at the first location of the interface, the second bonding stack is located at the second location of the interface, and the first bonding stack has a larger surface area than the second bonding stack.

12. The process according to claim 11, further comprising depositing at least a third bonding stack on the surface of the second wafer, wherein the third bonding stack is located at a third location of the interface at which the gap between the surfaces of the first and second wafers has a width that is between the width of the gap at the first and second locations, and the third bonding stack has a surface area that is between the surface areas of the first and second bonding stacks.

13. The process according to claim 11, further comprising applying a bonding pressure to the first and second wafers to cause the portion of the molten bonding material to flow into the first groove during the heating step.

14. The process according to claim 1, wherein the first wafer is a silicon-on-oxide wafer.

15. The process according to claim 1, further comprising fabricating a microelectromechanical system device on the first wafer prior to the aligning and mating step.

16. The process according to claim 15, further comprising fabricating a CMOS integrated circuit on the second wafer prior to the aligning and mating step, and the first groove prevents the molten bonding material from contacting an electrode of the CMOS integrated circuit.

17. The process according to claim 15, wherein the first bonding site is adjacent the microelectromechanical system device and the first groove prevents the molten bonding material from contacting the microelectromechanical system device.

18. The process according to claim 15, wherein the microelectromechanical system device comprises a proof mass and interdigitated fingers, and the first groove prevents the molten bonding material from contacting the interdigitated fingers of the microelectromechanical system device.

19. The process according to claim 1, wherein the first bonding stack contains gold and the first bonding structure contains a gold-silicon eutectic alloy.

20. The process according to claim 19, wherein the first wafer is formed of silicon and the gold-silicon eutectic alloy forms during the heating step by diffusion of silicon from the first wafer into the first bonding stack.

21. A wafer stack comprising:

first and second wafers;

a first bonding site on a surface of the first wafer;

a first groove in the surface of the first wafer, the first groove either surrounding the first bonding site or lying entirely within the first bonding site;

a first bonding structure bonded to the first bonding site of the first wafer and bonding the second wafer to the first wafer, at least a portion of the first bonding structure being present in the first groove in the surface of the first wafer.

22. The wafer stack according to claim 21, wherein the first groove surrounds and does not lie within the first bonding site.

23. The wafer stack according to claim 22, wherein the first groove is a continuous ring that surrounds the first bonding site.

24. The wafer stack according to claim 22, wherein the first groove is a segment of a first discontinuous ring that surrounds the first bonding site.

25. The wafer stack according to claim 24, further comprising a second discontinuous ring that surrounds the first bonding site and surrounds the first discontinuous ring.

26. The wafer stack according to claim 25, wherein at least one of the first and second discontinuous rings defines a gap that is overlapped by the other of the first and second discontinuous rings.

27. The wafer stack according to claim 22, further comprising at least a second bonding structure that surrounds the first groove in the surface of the first wafer, is bonded to a second bonding site of the first wafer, and bonds the second wafer to the first wafer, at least a portion of the second bonding structure being present in the first groove in the surface of the first wafer.

28. The wafer stack according to claim 22, further comprising forming a second groove that lies entirely within the first bonding site, contacts the first bonding structure, and contains a portion of the first bonding structure.

29. The wafer stack according to claim 21, wherein the first groove lies entirely within the first bonding site, contacts the first bonding structure, and contains a portion of the first bonding structure.

30. The wafer stack according to claim 21, wherein at least one of the surfaces of the first and second wafers has a radius of curvature of less than one hundred meters, and the first and second wafers define an interface therebetween and a gap between the surfaces of the first and second wafers that has a width that is greater at a first location of the interface than at a second location of the interface.

31. The wafer stack according to claim 30, further comprising a second bonding site on the surface of the first wafer and at least a second bonding structure bonded to the second bonding site and bonding the second wafer to the first wafer, wherein the first bonding structure is located at the first location of the interface, the second bonding structure is located at the second location of the interface, and the first bonding structure has a larger surface area than the second bonding structure.

32. The wafer stack according to claim 21, wherein the first wafer is a silicon-on-oxide wafer.

33. The wafer stack according to claim 21, further comprising a microelectromechanical system device on the first wafer.

34. The wafer stack according to claim 33, further comprising a CMOS integrated circuit on the second wafer, and the first groove is adjacent an electrode of the CMOS integrated circuit.

35. The wafer stack according to claim 34, wherein the first bonding site is adjacent the microelectromechanical system device.

36. The wafer stack according to claim 34, wherein the microelectromechanical system device comprises a proof mass and interdigitated fingers.

37. A wafer bonding process comprising:

providing first and second bonding sites on a surface of a first wafer;

depositing at least first and second bonding stacks on a surface of a second wafer, the first bonding stack having a larger surface area than the second bonding stack;

aligning and mating the first and second wafers so that the first and second bonding stacks on the second wafer contact the first and second bonding sites on the first wafer, respectively, the first and second wafers defining an interface therebetween and a gap between the surfaces of the first and second wafers, the gap having a width that is greater at a first location of the interface at which the first bonding stack and the first bonding site are located than at a second location of the interface at which the second bonding stack and the second bonding site are located; and

then

heating the first and second wafers to reflow the first and second bonding stacks on the second wafer, form a molten bonding material, and form first and second bonding structures that bond to the first and second bonding sites of the first wafer and bond the second wafer to the first wafer.

38. The process according to claim 37, wherein at least one of the surfaces of the first and second wafers has a radius of curvature of less than one hundred meters.

39. The process according to claim 37, further comprising depositing at least a third bonding stack on the surface of the second wafer, wherein the third bonding stack is located at a third location of the interface at which the gap between the surfaces of the first and second wafers has a width that is between the width of the gap at the first and second locations, and the third bonding stack has a surface area that is between the surface areas of the first and second bonding stacks.

40. The process according to claim 37, further comprising forming at least a first groove in the surface of the first wafer, the first groove either surrounding the first bonding site or lying entirely within the first bonding site, wherein during the heating step at least a portion of the molten bonding material flows into the first groove in the surface of the first wafer.