WAFER LEVEL PACKAGED MEMS INTEGRATED CIRCUIT

• US 20100072626A1
• Filed: 09/19/2008
• Published: 03/25/2010
• Est. Priority Date: 09/19/2008
• Status: Active Grant

• Current Assignee: Infineon Technologies AG
• Original Assignee: Infineon Technologies AG
• Inventors: Theuss, Horst, Schoen, Florian, Loehndorf, Markus
• Granted Patent: US 7,851,925 B2
• Time in Patent Office: Days
• US Class Current: 257/774
• CPC Class Codes: B81B 2201/0271 Resonators; ultrasonic resonators
• CPC Class Codes: B81B 2207/095 through the lid
• CPC Class Codes: B81C 1/00301 Connecting electric signal lines from the MEMS device with external electrical signal lines, e.g. through vias
• CPC Class Codes: H01L 2224/0401 Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
• CPC Class Codes: H01L 2224/13025 the bump connector being disposed on a via connection of the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/16145 the bodies being stacked
• CPC Class Codes: H01L 2224/16225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/17181 On opposite sides of the body
• CPC Class Codes: H01L 2224/45015 being circular
• CPC Class Codes: H01L 2224/45099 Material
• CPC Class Codes: H01L 2224/48145 the bodies being stacked
• CPC Class Codes: H01L 2224/48227 connecting the wire to a bond pad of the item
• CPC Class Codes: H01L 2225/06541 Conductive via connections through the device, e.g. vertical interconnects, through silicon via [TSV]
• CPC Class Codes: H01L 24/05 of an individual bonding area
• CPC Class Codes: H01L 24/16 of an individual bump connector
• CPC Class Codes: H01L 24/17 of a plurality of bump connectors
• CPC Class Codes: H01L 24/48 of an individual wire connector
• CPC Class Codes: H01L 25/0657 Stacked arrangements of devices
• CPC Class Codes: H01L 25/16 the devices being of types provided for in two or more different main groups of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. forming hybrid circuits
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00012 : Relevant to the scope of the group, the symbol of which is combined with the symbol of this group
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01078 : Platinum [Pt]
• CPC Class Codes: H01L 2924/01327 : Intermediate phases, i.e. intermetallics compounds
• CPC Class Codes: H01L 2924/10253 : Silicon [Si]
• CPC Class Codes: H01L 2924/14 : Integrated circuits
• CPC Class Codes: H01L 2924/1433 : Application-specific integrated circuit [ASIC]
• CPC Class Codes: H01L 2924/1461 : MEMS
• CPC Class Codes: H01L 2924/16235 : Connecting to a semiconductor or solid-state bodies, i.e. cap-to-chip
• CPC Class Codes: H01L 2924/207 : Diameter ranges

Abstract

A wafer-level packaged integrated circuit includes a semiconductor substrate including a first silicon layer. A micro-electromechanical system (MEMS) device is integrated into the first silicon layer. A thin-film deposited sealing member is deposited over the first silicon layer and is configured to seal a cavity in the first silicon layer. At least one additional layer is formed over the sealing member. At least one under bump metallization (UBM) is formed over the at least one additional layer.

Claims

1. A wafer-level packaged integrated circuit, comprising:

a semiconductor substrate including a first silicon layer;

a micro-electromechanical system (MEMS) device integrated into the first silicon layer;

a thin-film deposited sealing member deposited over the first silicon layer and configured to seal a cavity in the first silicon layer;

at least one additional layer formed over the sealing member; and

at least one under bump metallization (UBM) formed over the at least one additional layer.

2. The integrated circuit of claim 1, and further comprising:

at least one contact pad formed on the at least one additional layer; and

wherein the at least one UBM is formed on the at least one contact pad.

3. The integrated circuit of claim 1, and further comprising:

at least one conductive interconnection structure formed on the at least one UBM.

4. The integrated circuit of claim 3, wherein the at least one conductive interconnection structure comprises at least one solder element.

5. The integrated circuit of claim 1, wherein the sealing member comprises a plurality of thin-film deposited layers.

6. The integrated circuit of claim 1, wherein the at least one UBM comprises a plurality of stacked metal layers.

7. The integrated circuit of claim 1, wherein the at least one additional layer comprises at least one insulation layer formed over the sealing member, and at least one passivation layer formed over the at least one insulation layer.

8. The integrated circuit of claim 1, wherein the MEMS device is a MEMS resonator device.

9. The integrated circuit of claim 8, wherein the MEMS resonator device includes a silicon resonator structure and a plurality of electrodes formed in the first silicon layer.

10. The integrated circuit of claim 9, and further comprising:

at least one metal-filled via in contact with at least one of the electrodes, and extending through the at least one additional layer and electrically coupled to the at least one UBM.

11. The integrated circuit of claim 1, and further comprising:

an application specific integrated circuit (ASIC) integrated into the substrate and configured to control the MEMS device.

12. The integrated circuit of claim 1, wherein the MEMS device is a first MEMS resonator device, and wherein the integrated circuit further comprises:

at least one additional MEMS resonator device integrated into the first silicon layer in a side-by-side manner with the first MEMS resonator device.

13. The integrated circuit of claim 1, wherein the integrated circuit is configured to be electrically coupled to another integrated circuit in a face-to-face manner.

14. The integrated circuit of claim 1, wherein the integrated circuit is configured to be stacked together with at least one other integrated circuit and electrically coupled to the at least one other integrated circuit by metal-filled through vias.

15. The integrated circuit of claim 1, wherein the semiconductor substrate is a silicon-on-insulator (SOI) substrate including a buried oxide layer positioned between the first silicon layer and a second silicon layer.

16. A method of manufacturing a wafer-level packaged integrated circuit, comprising:

forming a micro-electromechanical system (MEMS) resonator device in a first silicon layer of a silicon-on-insulator (SOI) substrate;

performing a thin-film deposition of a sealing member over the first silicon layer, thereby sealing a cavity in the first silicon layer;

forming at least one additional layer over the sealing member;

forming at least one contact pad on the at least one additional layer; and

forming at least one under bump metallization (UBM) on the at least one contact pad.

17. The method of claim 16, and further comprising:

forming at least one conductive interconnection structure on the at least one UBM.

18. The method of claim 16, wherein the MEMS resonator device includes a silicon resonator structure and a plurality of electrodes formed in the first silicon layer.

19. The method of claim 18, and further comprising:

forming at least one metal-filled via in contact with at least one of the electrodes, and extending through the at least one additional layer and electrically coupled to the at least one contact pad.

20. A method of manufacturing wafer-level packaged integrated circuits, comprising:

forming a plurality of micro-electromechanical system (MEMS) resonator devices in a first silicon layer of a silicon-on-insulator (SOI) substrate;

performing a thin-film deposition of a sealing member over the first silicon layer for each MEMS resonator device, thereby sealing a cavity in the first silicon layer for each MEMS resonator device;

forming at least one additional layer over the sealing members;

forming at least one contact pad on the at least one additional layer for each MEMS resonator device;

forming at least one under bump metallization (UBM) on each contact pad; and

singulating the SOI substrate into a plurality of wafer-level packaged integrated circuits.