ARCHITECTURE AND INTERCONNECT SCHEME FOR PROGRAMMABLE LOGIC CIRCUITS

• US 20100073024A1
• Filed: 12/03/2009
• Published: 03/25/2010
• Est. Priority Date: 08/03/1993
• Status: Abandoned Application

• Current Assignee: Benjamin S. Ting
• Original Assignee: Benjamin S. Ting
• Inventors: Ting, Benjamin S.
• Application Number:
  US12/630,679
• Publication Number:
  US 20100073024A1
• Time in Patent Office: Days
• US Class Current: 326/38
• CPC Class Codes: H03K 19/17704 the logic functions being realised by the interconnection of rows and columns
• CPC Class Codes: H03K 19/17728 Reconfigurable logic blocks, e.g. lookup tables
• CPC Class Codes: H03K 19/17736 Structural details of routing resources
• CPC Class Codes: H03K 19/1778 Structural details for adapting physical parameters
• CPC Class Codes: H03K 19/17796 for physical disposition of blocks

Abstract

An architecture of hierarchical interconnect scheme for field programmable gate arrays (FPGAs). A first layer of routing network lines is used to provide connections amongst sets of block connectors where block connectors are used to provide connectability between logical cells and accessibility to the hierarchical routing network. A second layer of routing network lines provides connectability between different first layers of routing network lines. Additional layers of routing network lines are implemented to provide connectability between different prior layers of routing network lines. An additional routing layer is added when the number of cells is increased as the prior cell count in the array increases while the length of the routing lines and the number of routing lines also increases. Switching networks are used to provide connectability among same and different layers of routing network lines, each switching network composed primarily of program controlled passgates and, when needed, drivers.

Claims

1. A field programmable gate array architecture, comprising:

(a) a first logical cluster having a first span in a first dimension and having a second span in a second dimension, the cluster comprising a plurality of cells, each cell comprising;

an output,

at least one input, and

an input multiplexer coupled to each input;

(b) a first plurality of intraconnect conductors within the first and second spans, wherein the output of each cell in the first logical cluster is selectively coupleable to at least one input multiplexer coupled to each of the other cells in the first logical cluster by traversing a single one of the first plurality of intraconnect conductors;

(c) a second logical cluster having a third span in the first dimension and having a span in the second dimension equal to the second span, the cluster comprising a plurality of cells, each cell having;

an output,

at least one input, and

an input multiplexer coupled to each input;

(d) a second plurality of intraconnect conductors within the second and third spans, wherein the output of each cell in the second logical cluster is selectively coupleable to at least one input multiplexer coupled to each of the other cells in the second logical cluster by traversing a single one of the second plurality of intraconnect conductors;

(e) a third logical cluster having a fourth span in the first dimension and a span in the second dimension equal to the second span, the cluster comprising a plurality of cells, each cell having;

an output,

at least one input, and

an input multiplexer coupled to each input;

(f) a third plurality of intraconnect conductors within the second and fourth spans, wherein the output of each cell in the third logical cluster is selectively coupleable to at least one input multiplexer coupled to each of the other cells in the third logical cluster by traversing a single one of the third plurality of intraconnect conductors;

(g) a fourth logical cluster having a fifth span in the first dimension and a span in the second dimension equal to the second span, the cluster comprising a plurality of cells, each cell having;

an output,

at least one input, and

an input multiplexer coupled to each input;

(h) a fourth plurality of intraconnect conductors within the second and fifth spans, wherein the output of each cell in the fourth logical cluster is selectively coupleable to at least one input multiplexer of each of the other cells in the fourth logical cluster by traversing a single one of the fourth plurality of intraconnect conductors;

(i) a fifth plurality of routing conductors having a sixth span in the first dimension and a span in the second dimension equal to the second span, wherein the output of each cell in the first logical cluster is selectively coupleable to a plurality of input multiplexers in the second logical cluster; and

(j) a sixth plurality of routing conductors having a seventh span in the first dimension and a span in the second dimension equal to the second span, wherein the output of each cell in the third logical cluster is selectively coupleable to a plurality of input multiplexers in the fourth logical cluster,

(k) wherein at least one of the routing conductors in the fifth plurality of conductors is selectively coupleable to at least one of the routing conductors in the sixth plurality of conductors.