SYSTEM FOR SUBSTRATE POTENTIAL REGULATION DURING POWER-UP IN INTEGRATED CIRCUITS

• US 20100073075A1
• Filed: 11/30/2009
• Published: 03/25/2010
• Est. Priority Date: 11/12/2003
• Status: Active Grant

• Current Assignee: Meta Platforms, Inc. (f/k/a Facebook, Inc.)
• Original Assignee: Intellectual Ventures Funding LLC (Intellectual Ventures LLC)
• Inventors: Fu, Robert, Chen, Tien-Min
• Granted Patent: US 8,022,747 B2
• Time in Patent Office: Days
• US Class Current: 327/534
• CPC Class Codes: H01L 21/823892 with a particular manufacturing method of the wells or tubs, e.g. twin tubs, high energy well implants, buried implanted layers for lateral isolation [BILLI]
• CPC Class Codes: H01L 27/0222 Charge pumping, substrate bias generation structures
• CPC Class Codes: H01L 29/78 with field effect produced by an insulated gate H01L29/7725, H01L29/775, H01L29/778 take precedence
• CPC Class Codes: H03K 2217/0018 Special modifications or use of the back gate voltage of a FET

Abstract

An integrated circuit with body-bias inputs coordinated by a switch at initial power application. A switch coupled to the N-well bias and P-type substrate bias lines of an integrated circuit selectively couples the substrate to ground or the substrate bias supply, depending upon the state of the bias supply lines. During power-up and the initial application of the N-well bias, the substrate is coupled to ground to prevent a leakage induce rise in the substrate potential. Upon sensing the presence of the substrate bias potential on the substrate bias line, the switch couples the substrate to the substrate bias line instead of ground. In another embodiment, a switch indirectly senses the availability of the substrate bias potential by sensing a charge pump enable signal.

Claims

1. A circuit for regulating a substrate potential of an integrated circuit comprising:

a circuit element including;

a first input coupled to a first bias potential;

a second input coupled to a second bias potential;

a third input coupled to a charge pump enable line; and

an output terminal coupled to a substrate of said integrated circuit.

2. The circuit of claim 1, wherein said circuit element is operable to electrically couple said substrate to said second bias potential when said first bias potential is on and said charge pump enable line is off.

3. The circuit of claim 1, wherein said circuit element is operable to isolate said substrate from said second bias potential when said first bias potential is on and said charge pump enable line is on.

4. The circuit of claim 1, wherein said circuit element further comprises a fourth input coupled to a third bias potential.

5. The circuit of claim 4, wherein said circuit element is operable to electrically couple said substrate to said second bias potential when said third bias potential is on and said charge pump enable line is off.

6. The circuit of claim 4, wherein said circuit element is operable to electrically isolate said substrate from said second bias potential when said third bias potential is on and said charge pump enable line is on.

7. The circuit of claim 4, wherein said first bias potential comprises a first well bias.

8. The circuit of claim 4, wherein said second bias potential comprises a ground.

9. The circuit of claim 4, wherein said third bias potential comprises a second well bias.

10. The circuit of claim 1, wherein said circuit element comprises a switch.

11. An integrated circuit comprising:

a substrate;

a first well disposed in said substrate; and

a circuit element including;

a first input coupled to a first bias potential and to said first well;

a second input coupled to a second bias potential;

a third input coupled to a charge pump enable line; and

an output terminal coupled to said substrate.

12. The integrated circuit of claim 11, wherein said circuit element is operable to electrically couple said substrate to said second bias potential when said first bias potential is on and said charge pump enable line is off.

13. The integrated circuit of claim 11, wherein said circuit element is operable to isolate said substrate from said second bias potential when said first bias potential is on and said charge pump enable line is on.

14. The integrated circuit of claim 11, wherein said circuit element comprises a switch.

15. The integrated circuit of claim 14, wherein said switch is a single-pole, double throw (SPDT) switch.

16. The integrated circuit of claim 11, further comprising:

a second well disposed in said substrate.

17. The integrated circuit of claim 16, wherein said circuit element further comprises a fourth input coupled to a third bias potential and said second well.

18. The integrated circuit of claim 17, wherein said circuit element is operable to electrically couple said substrate to said second bias potential when said third bias potential is on and said charge pump enable line is off.

19. The integrated circuit of claim 17, wherein said circuit element is operable to electrically isolate said substrate from said second bias potential when said third bias potential is on and said charge pump enable line is on.

20. The integrated circuit of claim 17, wherein said first bias potential comprises a first well bias.

21. The integrated circuit of claim 17, wherein said second bias potential comprises a ground.

22. The integrated circuit of claim 17, wherein said third bias potential comprises a second well bias.