SYSTEM FOR SUBSTRATE POTENTIAL REGULATION DURING POWER-UP IN INTEGRATED CIRCUITS

• US 20100073076A1
• Filed: 11/30/2009
• Published: 03/25/2010
• Est. Priority Date: 11/12/2003
• Status: Active Grant

• Current Assignee: Meta Platforms, Inc. (f/k/a Facebook, Inc.)
• Original Assignee: Intellectual Ventures Funding LLC (Intellectual Ventures LLC)
• Inventors: Fu, Robert, Chen, Tien-Min
• Granted Patent: US 8,085,084 B2
• Time in Patent Office: Days
• US Class Current: 327/534
• CPC Class Codes: H01L 21/823892 with a particular manufacturing method of the wells or tubs, e.g. twin tubs, high energy well implants, buried implanted layers for lateral isolation [BILLI]
• CPC Class Codes: H01L 27/0222 Charge pumping, substrate bias generation structures
• CPC Class Codes: H01L 29/78 with field effect produced by an insulated gate H01L29/7725, H01L29/775, H01L29/778 take precedence
• CPC Class Codes: H03K 2217/0018 Special modifications or use of the back gate voltage of a FET

Abstract

An integrated circuit with body-bias inputs coordinated by a switch at initial power application. A switch coupled to the N-well bias and P-type substrate bias lines of an integrated circuit selectively couples the substrate to ground or the substrate bias supply, depending upon the state of the bias supply lines. During power-up and the initial application of the N-well bias, the substrate is coupled to ground to prevent a leakage induce rise in the substrate potential. Upon sensing the presence of the substrate bias potential on the substrate bias line, the switch couples the substrate to the substrate bias line instead of ground. In another embodiment, a switch indirectly senses the availability of the substrate bias potential by sensing a charge pump enable signal.

Claims

1. A method comprising:

accessing a first bias potential;

accessing a second bias potential; and

based on a voltage value of said first bias potential, coupling one of said first bias potential and said second bias potential to a substrate of an integrated circuit.

2. The method of claim 1, wherein said first bias potential comprises a substrate bias.

3. The method of claim 1, wherein said second bias potential comprises a ground.

4. The method of claim 1, wherein said coupling comprises:

coupling said second bias potential to said substrate if said voltage value of said first bias potential is off.

5. The method of claim 4, wherein said coupling further comprises:

coupling said first bias potential to said substrate if said voltage value of said first bias potential is on.

6. A method comprising:

accessing a first bias potential;

accessing a second bias potential;

accessing a third bias potential; and

based on voltage values of said first bias potential and said third bias potential, coupling one of said first bias potential and said second bias potential to a substrate of an integrated circuit.

7. The method of claim 6, wherein said first bias potential comprises a substrate bias.

8. The method of claim 6, wherein said second bias potential comprises a ground.

9. The method of claim 6, wherein said third bias potential comprises a well bias.

10. The method of claim 6, wherein said coupling comprises:

coupling said second bias potential to said substrate if said voltage value of said first bias potential is off and if said voltage value of said third bias potential is on.

11. The method of claim 10, wherein said coupling comprises:

coupling said first bias potential to said substrate if said voltage value of said first bias potential is on and if said voltage value of said third bias potential is on.

12. The method of claim 6, wherein said coupling comprises:

coupling said first bias potential to said substrate if said voltage value of said first bias potential is on and if said voltage value of said third bias potential is off.

13. The method of claim 6, wherein said coupling comprises:

coupling said second bias potential to said substrate if said voltage value of said first bias potential is on and if said voltage value of said third bias potential is off.

14. A method comprising:

accessing a charge pump enable line;

accessing a first bias potential;

coupling a charge pump output to a substrate of an integrated circuit; and

based on a voltage value of said charge pump enable line, allowing a connection between said first bias potential and said substrate.

15. The method of claim 14, wherein said first bias potential comprises a ground.

16. The method of claim 14, wherein said substrate comprises a P-type substrate.

17. The method of claim 14, wherein said allowing comprises:

allowing said connection between said first bias potential and said substrate if said voltage value of said charge pump enable line is off.

18. The method of claim 14, further comprising:

accessing a second bias potential.

19. The method of claim 18, wherein said second bias potential comprises a well bias.

20. The method of claim 18, further comprising:

based on voltage values of said charge pump enable line and said second bias potential, allowing said connection between said first bias potential and said substrate.