MEMORY DEVICES AND ACCESS METHODS THEREOF

• US 20100077132A1
• Filed: 10/29/2008
• Published: 03/25/2010
• Est. Priority Date: 09/25/2008
• Status: Active Grant

• Current Assignee: Silicon Motion Incorporated California (Silicon Motion)
• Original Assignee: Silicon Motion Incorporated California (Silicon Motion)
• Inventors: Hung, Chi-Hsiang
• Granted Patent: US 8,448,046 B2
• Time in Patent Office: Days
• US Class Current: 711/103
• CPC Class Codes: G06F 11/1068 in sector programmable memories, e.g. flash disk G06F11/1072 takes precedence
• CPC Class Codes: G06F 12/0246 in block erasable memory, e.g. flash memory
• CPC Class Codes: G06F 2212/7211 Wear leveling
• CPC Class Codes: G11C 16/349 Arrangements for evaluating degradation, retention or wearout, e.g. by counting erase cycles
• CPC Class Codes: G11C 2029/0411 Online error correction

Abstract

Methods and devices capable of erasing a flash memory evenly are provided, in which a flash memory comprises a data region with a plurality of data blocks and a spare region with a plurality of spare blocks, and a controller retrieves a corresponding data with a check code from a first data block of the flash memory according to a read command from a host, performs a predetermined check to the corresponding data by the check code, determines whether an error is correctable when a check result of the predetermined check represents that the error has occurred, and increases an erase count of the first data block by a predetermined value when the error is correctable.

Claims

1. An access method for a flash memory, wherein the flash memory comprises a data region and a spare region, the data region comprises a plurality of data blocks and the spare region comprises a plurality of spare blocks, comprising:

retrieving a corresponding data with a check code from a first data block of the flash memory according to a read command from a host;

performing a predetermined check to the corresponding data by the check code;

determining whether an error is correctable when a check result of the predetermined check represents that the error has occurred; and

increasing an erase count of the first data block by a predetermined value when the error is correctable.

2. The method as claimed in claim 1, further comprising marking the first data block as a failed block when the error is uncorrectable.

3. The method as claimed in claim 1, wherein the check code is an error correction code (ECC).

4. The method as claimed in claim 1, wherein the predetermined value exceeds two.

5. The method as claimed in claim 1, further comprising:

receiving data corresponding to a logical address linked to a second data block of the data region when receiving a write command from the host;

popping a spare block from the spare region; and

writing the data into the popped spare block and linking a physical address of the popped spare block to the logic address.

6. The method as claimed in claim 5, further comprising performing data integration to the data blocks of the data region before popping the spare block.

7. The method as claimed in claim 5, further comprising:

erasing the second data block; and

pushing the second data block into the spare region.

8. An access method for a flash memory, wherein the flash memory is divided into a data region with a plurality of data blocks and a spare region with a plurality of spare blocks, comprising:

retrieving a corresponding data with a check code from a first data block of the flash memory according to a read command from a host;

performing a predetermined check to the corresponding data by the check code;

determining whether an error is correctable when a check result of the predetermined check represents that the error has occurred;

increasing an erase count of the first data block by a predetermined value when the error is correctable;

receiving data corresponding to a logical address linked to a second data block of the data region when receiving a write command from the host;

popping a first spare block from the spare region; and

writing data stored in a third data block to the first spare block and re-mapping the third data block and the first spare block when an erase count of the first spare block reaches a default value and the data region has the third data block with an erase count of zero.

9. The method as claimed in claim 8, further comprising decreasing the erase count of the all data blocks in the data region and the all spare blocks in the spare region by one, when the erase count of the first spare block reaches the default value and the data region does not have the third data block with the erase count of zero.

10. The method as claimed in claim 9, further comprising:

popping a second spare block from the spare region; and

writing the data corresponding to the logical address into the second spare block and linking a physical address of the second spare block to the logic address, when the erase count of the second spare block is less than the default value.

11. A memory device, comprising:

a flash memory comprising a data region with a plurality of data blocks and a spare region with a plurality of spare blocks; and

a controller retrieving a corresponding data with a check code from a first data block of the flash memory according to a read command from a host, performing a predetermined check to the corresponding data by the check code, determining whether an error is correctable when a check result of the predetermined check represents that the error has occurred, and increasing an erase count of the first data block by a predetermined value when the error is correctable.

12. The memory device as claimed in claim 11, wherein the controller marks the first data block as a failed block when the error is uncorrectable.

13. The memory device as claimed in claim 11, wherein the check code is an error correction code (ECC).

14. The memory device as claimed in claim 11, wherein the predetermined value exceeds two.

15. The memory device as claimed in claim 11, wherein the controller receives data corresponding to a logical address linked to a second data block when receiving a write command from the host, and the controller pops a spare block from the spare region, and writes the data into the popped spare block and links a physical address of the popped spare block to the logical address when the erase count of the popped spare block is less than a default value.

16. The memory device as claimed in claim 15, wherein the controller further performs a data integration to the data blocks of the data region before popping the spare block.

17. The memory device as claimed in claim 15, wherein the controller erases the second data block and pushes the erased second data block into the spare region when the erase count of the popped spare block is less than the default value.

18. The memory device as claimed in claim 15, wherein, when an erase count of the popped spare block reaches the default value and the data region has a third data block with an erase count of zero, the controller writes data stored in the third data block to the popped spare block and re-maps the third data block and the popped spare block.

19. The memory device as claimed in claim 18, wherein, when the erase count of the first spare block reaches the default value and the data region does not have the third data block with the erase count of zero, the controller decreases the erase count of the all data blocks in the data region and the all spare blocks in the spare region by one.

20. The memory device as claimed in claim 18, wherein the controller further erases the third data block and pushes the erased third data block into the spare region, when the erase count of the popped spare block reaches the default value and the data region has the third data block with the erase count of zero.