Flash Memory Integrated Circuit with Compression/Decompression CODEC

• US 20100077133A1
• Filed: 07/17/2009
• Published: 03/25/2010
• Est. Priority Date: 09/11/2008
• Status: Active Grant

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Samsung Electronics Co. Ltd.
• Inventors: Jeon, Jun Young
• Granted Patent: US 9,236,129 B2
• Time in Patent Office: Days
• US Class Current: 711/103
• CPC Class Codes: G11C 16/10 Programming or data input circuits
• CPC Class Codes: G11C 16/26 Sensing or reading circuits; Data output circuits

Abstract

Provided is a flash memory integrated circuit with a compression codec. The flash memory integrated circuit may simultaneously include a memory block and a compression codec circuit. The compression codec circuit may compress input data. A controller circuit may store the compressed input data in at least one page that is included in the memory block. Through this, it is possible to enhance a usage efficiency of a flash memory.

Claims

1. A flash memory integrated circuit with a compression codec, comprising:

at least one memory block to include a plurality of pages;

a compression codec circuit to compress input data; and

a controller circuit to generate a control signal in order to sequentially write the compressed input data in at least one page among the plurality of pages.

2. The flash memory integrated circuit of claim 1, wherein the compression codec circuit compresses the input data according to a predetermined compression algorithm.

3. The flash memory integrated circuit of claim 1, wherein the input data is multimedia data.

4. The flash memory integrated circuit of claim 1, wherein the at least one memory block is a memory block of a NAND flash memory.

5. The flash memory integrated circuit of claim 1,wherein the controller circuit generates the control signal to control voltages to be applied to a word line or a bit line that is connected to the at least one page.

6. The flash memory integrated circuit of claim 1, further comprising:

a type decision circuit to determine whether the input data is compressed,

wherein the compression codec circuit compresses the input data when the input data is not compressed.

7. The flash memory integrated circuit of claim 6, wherein the type decision circuit comprises comparing a type of the input data with predetermined types to determine whether the input data is compressed.

8. The flash memory integrated circuit of claim 6, wherein:

the type decision circuit provides a logic value corresponding to the determination, and

the compression codec circuit compresses the input data according to the provided logic value.

9. The flash memory integrated circuit of claim 1, wherein the controller circuit generates the control signal in order to write, in the at least one memory block, identification information capable of identifying the compressed input data.

10. A flash memory integrated circuit with a compression codec, comprising:

at least one memory block to include a plurality of pages;

a controller circuit to generate a control signal in order to read compressed data that is written in at least one page among the plurality of pages; and

a compression codec circuit to decompress the read compressed data according to a predetermined algorithm,

wherein the compressed data is written in the at least one page by the compression codec circuit.

11. The flash memory integrated circuit of claim 10, wherein:

identification information capable of identifying the compressed data is further stored in the at least one memory block, and

the compression codec circuit decompresses the read compressed data according to the identification information.

12. A method of operating a flash memory with a compression codec, the method comprising:

compressing input data of the flash memory according to a predetermined compression algorithm; and

generating a control signal in order to write the compressed input data in at least one page among a plurality of pages that is included in at least one memory block of the flash memory.

13. The method of claim 12, further comprising:

determining whether the input data is compressed,

wherein the compressing of the input data comprises compressing the input data when the input data is not compressed.

14. The method of claim 12, wherein the generating of the control signal comprises generating the control signal in order to further write, in the at least one memory block, identification information capable of identifying the compressed input data.

17. A computer-readable recording medium storing a program for causing a processor to implement the method of claim 12.

15. A method of operating a flash memory with a compression codec, the method comprising:

generating a control signal in order to read compressed data that is written in at least one page among a plurality of pages included in at least one memory block of the flash memory; and

decompressing, by a compression codec circuit, the read compressed data according to a predetermined algorithm,

wherein the compressed data is written in the at least one page by the compression codec circuit.

16. The method of claim 15, wherein:

identification information capable of identifying the compressed data is further stored in the at least one memory block, and

the decompressing of the read compressed data comprises decompressing the read compressed data according to the identification information.