LOW POWER ELECTRONIC SYSTEM ARCHITECTURE USING NON-VOLATILE MAGNETIC MEMORY

• US 20100077244A1
• Filed: 09/23/2008
• Published: 03/25/2010
• Est. Priority Date: 09/23/2008
• Status: Active Grant

• Current Assignee: Qualcomm, Inc.
• Original Assignee: Qualcomm, Inc.
• Inventors: Kang, Seung H., Nowak, Matthew Michael, Chua-Eoan, Lew
• Granted Patent: US 8,719,610 B2
• Time in Patent Office: Days
• US Class Current: 713/324
• CPC Class Codes: G06F 1/3203 Power management, i.e. event-based initiation of a power-saving mode
• CPC Class Codes: G06F 1/3275 Power saving in memory, e.g. RAM, cache
• CPC Class Codes: G11C 11/16 using elements in which the storage effect is based on magnetic spin effect
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management
• CPC Class Codes: Y02D 30/50 in wire-line communication networks, e.g. low power modes or reduced link rate

Abstract

A computing system includes at least one functional unit and a magnetic random access memory (MRAM) block coupled to the at least one functional unit. The MRAM block is configured to store a functional state of the at least one functional unit during a power down state of the at least one functional unit.

Claims

1. A computing system comprising:

at least one functional unit; and

a magnetoresistive random access memory (MRAM) block coupled to the at least one functional unit, the MRAM block configured to store a functional state of the at least one functional unit during a power down state of the at least one functional unit.

2. The computing system of claim 1 further comprising:

a random access memory (RAM) block coupled to the at least one functional unit and the MRAM block, wherein the RAM block is configured to store a portion of the functional state of the at least one functional unit during a power on state of the at least on functional unit, and wherein the MRAM block is further configured to store the portion during the power down state.

3. The computing system of claim 2 further comprising:

a data mover block configured to transfer the portion of the functional state located in the RAM into the MRAM block during the power down state.

4. The computer system of claim 1 wherein the MRAM block is a spin torque transfer (STT) MRAM block.

5. The computing system of claim 1 wherein the functional state comprises a plurality of data representing the functional state of the at least one functional unit.

6. The computing system of claim 1 wherein the MRAM block comprises an STT MRAM chip and the at least one functional unit comprises at least one functional unit chip, and wherein the STT MRAM chip and the at least one functional unit chip are stacked on top of one another and bonded together with one or more conductive bonding pads.

7. The computing system of claim 1 wherein the MRAM block is coupled to the at least one functional unit by embedding the MRAM block into a silicon substrate of the at least one functional unit during fabrication of the at least one functional unit.

8. The computing system of claim 1 wherein the MRAM block is coupled to the at least one functional unit through a transmission bus on the computing system.

9. A method comprising:

receiving a standby signal requesting one or more functional units of a computing system to enter a standby state;

responsive to receiving the standby signal, storing at least a portion of a current operational state of the one or more functional units in a magnetic random access memory (MRAM) coupled to the one or more functional units; and

removing power from the one or more functional units after the current operational state is stored.

10. The method of claim 9 further comprising:

receiving a wake-up signal requesting the one or more functional units in the standby mode to enter an operating mode;

responsive to receiving the wake-up signal, restoring the power to the one or more functional units in the standby mode; and

reinstating the current operational state to the one or more functional units.

11. The method of claim 9 wherein the storing comprises:

scanning a processing path of the one or more functional units for ones of a plurality of data defining at least a portion of the current operational state;

transmitting the ones of the plurality of data from the one or more functional units to the MRAM; and

transferring additional ones of the plurality of data defining another portion of the current operational state from a random access memory (RAM) coupled within the one or more functional units to the MRAM.

12. The method of claim 11 further comprising:

receiving a wake-up signal requesting the one or more functional units in the standby mode to enter an operating mode;

in response to the wake-up signal, restoring the power to the one or more functional units in the standby mode;

loading the ones of the plurality of data from the MRAM into the processing path of the one or more functional units; and

reinstating the additional ones of the plurality of data from the MRAM into the RAM.

13. The method of claim 9 wherein the storing comprises:

storing ones of a plurality of data defining at least a portion of the current operational state located in a processing path of the one or more functional units in one or more magnetic memories associated with one or more latches in the processing path; and

transferring additional ones of the plurality of data defining another portion of the current operational state from a random access memory (RAM) coupled within the one or more functional units to the MRAM.

14. The method of claim 13 further requiring:

receiving a wake-up signal requesting the one or more functional units in the standby mode to enter an operating mode;

in response to the wake-up signal, restoring the power from the power supply to the one or more functional units in the standby mode;

loading the ones of the plurality of data from the one or more magnetic memories into the processing path of the one or more functional units; and

reinstating the additional ones of the plurality of data from the MRAM into the RAM.

15. The method of claim 9 wherein the removing the power comprises one or both of:

switching off a power supply coupled to the one or more functional units; and

creating an open circuit between the power supply and the one or more functional units.

16. A system comprising:

means for receiving a standby signal requesting one or more functional units of a computing system to enter a standby state;

responsive to the standby signal, means for storing at least a portion of a current operational state of the one or more functional units in a magnetic random access memory (MRAM) coupled to the one or more functional units;

means for removing power from the one or more functional units after the current operational state is stored;

means for receiving a wake-up signal requesting the one or more functional units in the standby mode to enter an operating mode;

responsive to the wake-up signal, means for restoring the power to the one or more functional units in the standby mode; and

means for reinstating the current operational state to the one or more functional units.

17. The system of claim 16 wherein the means for storing comprises:

means for scanning a processing path of the one or more functional units for ones of a plurality of data defining at least a portion of the current operational state;

means for transmitting the ones of the plurality of data from the one or more functional units to the MRAM; and

means for transferring additional ones of the plurality of data defining another portion of the current operational state from a random access memory (RAM) coupled within the one or more functional units to the MRAM.

18. The system of claim 17 further comprising:

means for loading the ones of the plurality of data from the MRAM into the processing path of the one or more functional units; and

means for reinstating the additional ones of the plurality of data from the MRAM into the RAM.

19. The system of claim 16 wherein the means for storing comprises:

means for storing ones of a plurality of data defining at least a portion of the current operational state located in a processing path of the one or more functional units in one or more magnetic memories associated with one or more latches in the processing path; and

means for transferring additional ones of the plurality of data defining another portion of the current operational state from a random access memory (RAM) coupled within the one or more functional units to the MRAM.

20. The system of claim 19 further comprising:

means for loading the ones of the plurality of data from the one or more magnetic memories into the processing path of the one or more functional units; and

means for reinstating the additional ones of the plurality of data from the MRAM into the RAM.

21. The system of claim 16 wherein the means for removing the power comprises one or both of:

means for switching off a power supply coupled to the one or more functional units; and

means for creating an open circuit between the power supply and the one or more functional units.