Reset Signal Generation Circuit and Semiconductor Device

• US 20100078488A1
• Filed: 09/29/2009
• Published: 04/01/2010
• Est. Priority Date: 09/30/2008
• Status: Active Grant

• Current Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Original Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Inventors: Nagatsuka, Shuhei
• Granted Patent: US 8,353,460 B2
• Time in Patent Office: Days
• US Class Current: 235/492
• CPC Class Codes: G06K 19/0723 the record carrier comprising an arrangement for non-contact communication, e.g. wireless communication circuits on transponder cards, non-contact smart cards or RFIDs

Abstract

An object is to provide a reset signal generation circuit which has a simple circuit configuration without hysteresis characteristics so as not to occupy a larger area, and is resistant to noise and can surely generate a power-on reset signal; and to provide a semiconductor device including the reset signal generation circuit. The reset signal generation circuit includes a first buffer circuit, a low pass filter, a resistor, and a second buffer circuit. An output terminal of the first buffer circuit is electrically connected to an input terminal of the low pass filter. An output terminal of the low pass filter is electrically connected to one terminal of the resistor and an input terminal of the second buffer circuit. A constant potential is supplied to the other terminal of the resistor.

Claims

1. A reset signal generation circuit comprising:

a first buffer circuit;

a low pass filter;

a resistor; and

a second buffer circuit,

wherein an output terminal of the first buffer circuit is electrically connected to an input terminal of the low pass filter,

wherein an output terminal of the low pass filter is electrically connected to one terminal of the resistor and an input terminal of the second buffer circuit, and

wherein a constant potential is supplied to the other terminal of the resistor.

2. The reset signal generation circuit according to claim 1,

wherein a signal output from the first buffer circuit is delayed by the low pass filter,

wherein a waveform of the delayed signal is shaped by the second buffer circuit, and

wherein electric charge held in the low pass filter is discharged through the resistor when supply of the constant potential is stopped.

3. A reset signal generation circuit comprising:

first to third buffer circuits;

first and second low pass filters; and

first and second resistors,

wherein an output terminal of the first buffer circuit is electrically connected to an input terminal of the first low pass filter,

wherein an output terminal of the first low pass filter is electrically connected to one terminal of the first resistor and an input terminal of the second buffer circuit,

wherein a constant potential is supplied to the other terminal of the first resistor,

wherein an output terminal of the second buffer circuit is electrically connected to an input terminal of the second low pass filter,

wherein an output terminal of the second low pass filter is electrically connected to one terminal of the second resistor and an input terminal of the third buffer circuit, and

wherein a constant potential is supplied to the other terminal of the second resistor.

4. The reset signal generation circuit according to claim 3,

wherein a signal output from the first buffer circuit is delayed by the first low pass filter,

wherein a waveform of the delayed signal is shaped by the second buffer circuit,

wherein a signal output from the second buffer circuit is delayed by the second low pass filter,

wherein a waveform of the signal delayed by the second low pass filter is shaped by the third buffer circuit, and

wherein electric charge held in the first low pass filter is discharged through the first resistor and electric charge held in the second low pass filter is discharged through the second resistor when supply of the constant potential is stopped.

5. A semiconductor device comprising:

an antenna;

a rectifier circuit configured to generate an internal power supply from a signal received by the antenna;

a demodulation circuit configured to demodulate a signal received by the antenna;

a reset signal generation circuit configured to generate a reset signal from the internal power supply;

a signal processing circuit configured to perform predetermined operation using the internal power supply, a demodulation signal generated in the demodulation circuit, and the reset signal; and

a modulation circuit configured to modulate a response signal generated in the signal processing circuit into a wireless signal,

wherein the reset signal generation circuit includes a first buffer circuit, a low pass filter, a resistor, and a second buffer circuit,

wherein an input terminal of the first buffer circuit is electrically connected to an output terminal of the rectifier circuit,

wherein an output terminal of the first buffer circuit is electrically connected to an input terminal of the low pass filter,

wherein an output terminal of the low pass filter is electrically connected to one terminal of the resistor and an input terminal of the second buffer circuit,

wherein an output terminal of the second buffer circuit is electrically connected to an input terminal of the signal processing circuit, and

wherein a constant potential is supplied to the other terminal of the resistor.

6. The semiconductor device according to claim 5,

wherein a signal output from the first buffer circuit is delayed by the low pass filter,

wherein a waveform of the delayed signal is shaped by the second buffer circuit, and

wherein electric charge held in the reset signal generation circuit is discharged through the resistor when supply of the constant potential is stopped.

9. The semiconductor device according to claim 5, being a passive wireless tag driven by generating the internal power supply by using electronic power of an electromagnetic wave from a reader/writer.

10. The semiconductor device according to claim 6, being a passive wireless tag driven by generating the internal power supply by using electronic power of an electromagnetic wave from a reader/writer.

7. A semiconductor device comprising:

an antenna;

a rectifier circuit configured to generate an internal power supply from a signal received by the antenna;

a demodulation circuit configured to demodulate a signal received by the antenna;

a reset signal generation circuit configured to generate a reset signal from the internal power supply;

a signal processing circuit configured to perform predetermined operation using the internal power supply, a demodulation signal generated in the demodulation circuit, and the reset signal; and

a modulation circuit configured to modulate a response signal generated in the signal processing circuit into a wireless signal,

wherein the reset signal generation circuit includes first to third buffer circuits, first and second low pass filters, and first and second resistors,

wherein an input terminal of the first buffer circuit is electrically connected to an output terminal of the rectifier circuit,

wherein an output terminal of the first buffer circuit is electrically connected to an input terminal of the first low pass filter,

wherein an output terminal of the first low pass filter is electrically connected to one terminal of the first resistor and an input terminal of the second buffer circuit,

wherein a constant potential is supplied to the other terminal of the first resistor,

wherein an output terminal of the second buffer circuit is electrically connected to an input terminal of the second low pass filter,

wherein an output terminal of the second low pass filter is electrically connected to one terminal of the second resistor and an input terminal of the third buffer circuit,

wherein an output terminal of the third buffer circuit is electrically connected to an input terminal of the signal processing circuit, and

wherein a constant potential is supplied to the other terminal of the second resistor.

8. The semiconductor device according to claim 7,

wherein a signal output from the first buffer circuit is delayed by the first low pass filter,

wherein a waveform of the delayed signal is shaped by the second buffer circuit,

wherein a signal output from the second buffer circuit is delayed by the second low pass filter,

wherein a waveform of the signal delayed by the second low pass filter is shaped by the third buffer circuit, and

wherein electric charge held in the reset signal generation circuit is discharged through the first and second resistors when supply of the constant potential is stopped.

11. The semiconductor device according to claim 7, being a passive wireless tag driven by generating the internal power supply by using electronic power of an electromagnetic wave from a reader/writer.

12. The semiconductor device according to claim 8, being a passive wireless tag driven by generating the internal power supply by using electronic power of an electromagnetic wave from a reader/writer.