SEMICONDUCTOR DEVICE

• US 20100078635A1
• Filed: 05/14/2009
• Published: 04/01/2010
• Est. Priority Date: 09/29/2008
• Status: Abandoned Application

• Current Assignee: Hitachi, Ltd.
• Original Assignee: Hitachi, Ltd.
• Inventors: Kuroda, Yuki, Mizuno, Hiroyuki, Saen, Makoto, Ito, Kiyoto
• Application Number:
  US12/465,819
• Publication Number:
  US 20100078635A1
• Time in Patent Office: Days
• US Class Current: 257/48
• CPC Class Codes: G11C 29/02 Detection or location of defective auxiliary circuits, e.g. defective refresh counters
• CPC Class Codes: G11C 29/025 in signal lines
• CPC Class Codes: G11C 5/02 Disposition of storage elements, e.g. in the form of a matrix array
• CPC Class Codes: G11C 5/04 Supports for storage elements , e.g. memory modules; Mounting or fixing of storage elements on such supports
• CPC Class Codes: H01L 2224/32145 the bodies being stacked
• CPC Class Codes: H01L 2224/48091 Arched
• CPC Class Codes: H01L 2224/48227 connecting the wire to a bond pad of the item
• CPC Class Codes: H01L 2225/0651 Wire or wire-like electrical connections from device to substrate
• CPC Class Codes: H01L 2225/06513 Bump or bump-like direct electrical connections between devices, e.g. flip-chip connection, solder bumps
• CPC Class Codes: H01L 2225/06541 Conductive via connections through the device, e.g. vertical interconnects, through silicon via [TSV] manufacturing via connections per se H01L21/76898
• CPC Class Codes: H01L 2225/06572 Auxiliary carrier between devices, the carrier having an electrical connection structure
• CPC Class Codes: H01L 24/73 Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
• CPC Class Codes: H01L 25/0657 Stacked arrangements of devices
• CPC Class Codes: H01L 25/18 the devices being of types provided for in two or more different subgroups of the same main group of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N
• CPC Class Codes: H01L 2924/00014 the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01006 Carbon [C]
• CPC Class Codes: H01L 2924/01033 Arsenic [As]
• CPC Class Codes: H01L 2924/01082 Lead [Pb]
• CPC Class Codes: H01L 2924/15311 being a ball array, e.g. BGA
• CPC Class Codes: H01L 2924/3011 Impedance

Abstract

As the transfer between a processor LSI and a memory has been increasing year by year, there is a demand for increasing the traffic amount and reducing the power required for communication. With this being the condition, a method of stacking LSIs thereby reducing the communication distance is being contemplated. However, the inventors have found that the reduction of cost in the stacking process and the increase in the degree of freedom of selecting the memory LSI to be stacked are required for a simple stacking of processor LSIs and memory LSIs as so far practiced. An external communication LSI including a circuit for performing the communication with the outside of the stacked LSI at a high rate of more than 1 GHz; a processor LSI including a general purpose CPU etc.; and a memory LSI including a DRAM etc. are stacked in this order and those LSIs are connected with one another with a through silicon via to enable a high speed and high volume communication at a shortest path. Further, an interposer for facilitating the connection with the processor LSI is connected to the input terminal of the memory LSI to be stacked thereby increasing the degree of freedom in selecting memories.

Claims

1. A semiconductor device, comprising:

a package board;

a first LSI connected to the package board and including a communication circuit performing communication through the package board;

a second LSI provided above the first LSI and performing arithmetic processing;

a third LSI provided above the second LSI and including a first storage device storing a result of arithmetic processing of the second LSI, the first storage device including a plurality of first memory cells provided at intersection points of a plurality of first bit lines and a plurality of first word lines; and

a first through silicon via provided so as to pass through the second LSI and electrically connecting the first, second, and third LSIs with one another.

2. The semiconductor device according to claim 1, further comprising:

an interposer layer provided between the second LSI and the third LSI and connecting between the second LSI and the third LSI with wiring.

3. The semiconductor device according to claim 2, wherein

the third LSI is configured such that its surface on which circuitry is disposed has a first area different from a second area of a surface of the second LSI on which circuitry is disposed.

4. The semiconductor device according to claim 2, wherein

the third LSI is configured such that the position of its connection terminal is different from that of a connection terminal of the second LSI.

5. The semiconductor according to claim 1, wherein

the first LSI includes a first test circuit;

the second LSI includes a second test circuit; and

the first test circuit and the second test circuit are adapted to perform a communication test between the first LSI and the second LSI through the first through silicon via.

6. The semiconductor device according to claim 1, wherein

the plurality of first memory cells are DRAM cells.

7. The semiconductor device according to claim 1, wherein

a first power supply is provided to the first LSI, the second LSI, and the third LSI through the first through silicon via.

8. The semiconductor device according to claim 1, further comprising:

a first bonding wire connecting the package board with the second LSI; and

a second bonding wire connecting the package board with the third LSI, wherein

a second power supply is provided to the second LSI through the first bonding wire, and

a third power supply is provided to the third LSI through the second bonding wire.

9. The semiconductor device according to claim 1, wherein

the second LSI receives communication data from the first LSI through the first through silicon via, and

the second LSI stores processed data resulting from arithmetic processing of the communication data, into the plurality of first memory cells through the first through silicon via.

10. The semiconductor device according to claim 1, further comprising:

a fourth LSI provided between the first LSI and the second LSI, and performing arithmetic processing and storing a result of the arithmetic processing into the first storage device, wherein

when the second LSI requests the third LSI of the transmission/reception of first data, the second LSI causes a first request signal corresponding to the transmission/reception of the first data to include a first identifier indicating that the source of the first request signal is the second LSI, and

when the fourth LSI requests the third LSI of the transmission/reception of second data, the fourth LSI causes a second request signal corresponding to the transmission/reception of the second data to include a second identifier for indicating that the source of a second request signal is the fourth LSI.

11. The semiconductor device according to claim 1, further comprising:

a fifth LSI provided above the third LSI and including a second storage device storing the result of arithmetic processing of the second LSI;

the second storage device including a plurality of second memory cells provided at intersection points of a plurality of second bit lines and a plurality of second word lines, wherein

when the second LSI requests the third LSI of the transmission/reception of third data, the second LSI causes a third request signal corresponding to the transmission/reception of the third data to include a third identifier for indicating that the destination of the third request signal is the third LSI, and

when the second LSI request the fifth LSI of the transmission/reception of fourth data, the second LSI causes a fourth request signal corresponding to the transmission/reception of the fourth data to include a fourth identifier for indicating that the destination of the fourth request signal is the fifth LSI.

12. A semiconductor device, comprising:

a package board;

a first LSI connected to the package board and including a communication circuit performing communication via the package board;

a second LSI provided above the first LSI and performing arithmetic processing using data from the communication circuit;

a first through silicon via configured to pass through the second LSI and for electrically connecting the first and second LSIs; and

an interposer layer provided above the second LSI, electrically connected to the first through silicon via, and provided on its top with a connection terminal for connecting another circuit.

13. The semiconductor device according to claim 12, wherein

the first LSI includes a first communication section performing communication with an LSI outside the first LSI;

the second LSI includes a second communication section performing communication with an LSI outside the second LSI; and

the interposer layer connects the first communication section or the second communication section with an LSI other than the first LSI and other than the second LSI.

14. The semiconductor device according to claim 12, further comprising

a third LSI including a first storage device storing result of arithmetic processing of the second LSI, the first storage device including a plurality of first memory cells at intersection points of a plurality of first bit lines and a plurality of first word lines, wherein

the interposer layer is adapted to electrically connect the first LSI and the second LSI with the third LSI.

15. The semiconductor device according to claim 12, wherein

the first LSI includes a first test circuit;

the second LSI includes a second test circuit; and

the first test circuit and the second test circuit are adapted to perform a communication test between the first LSI and the second LSI through the first through silicon via.

16. The semiconductor device according to claim 12, wherein

the plurality of first memory cells are DRAM cells.

17. A method of manufacturing a semiconductor device in which a plurality of LSIs are stacked, the method comprising:

a first step of stacking a first LSI above a package board, the first LSI including a communication circuit for performing communication via the package board;

after the first step, a second step of stacking a second LSI above the first LSI, the second LSI being adapted to perform arithmetic processing using data from the communication circuit;

after the second step, a third step of providing an interposer layer above the second LSI, the interposer layer being adapted to connect between the first LSI or the second LSI and an LSI other than the first LSI and other than the second LSI with wiring; and

after the third step, a fourth step of providing a first through silicon via configured to pass through the second LSI and adapted to electrically connect the first LSI and the second LSI with each other.

18. The method of manufacturing a semiconductor device according to claim 17, further comprising:

after the fourth step, a fifth step of testing communication between the first LSI and the second LSI via the first through silicon via.

19. The method of manufacturing a semiconductor device according to claim 17, further comprising

after the fourth step, a sixth step of providing a third LSI including a first storage device for storing a result of arithmetic processing of the second LSI, the first storage device being connected with the first LSI or the second LSI by the interposer layer and having a plurality of first memory cells provided at intersection points of a plurality of first bit liens and a plurality of first word lines.