SEMICONDUCTOR SENSOR STRUCTURES WITH REDUCED DISLOCATION DEFECT DENSITIES AND RELATED METHODS FOR THE SAME

• US 20100078680A1
• Filed: 09/24/2009
• Published: 04/01/2010
• Est. Priority Date: 09/24/2008
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: AmberWave Systems Corporation
• Inventors: Lochetefeld, Anthony, Fiorenza, James G., Sheen, Calvin, Cheng, Zhiyuan
• Granted Patent: US 8,253,211 B2
• Time in Patent Office: Days
• US Class Current: 257/184
• CPC Class Codes: H01L 21/02381 Silicon, silicon germanium, germanium
• CPC Class Codes: H01L 21/02521 Materials
• CPC Class Codes: H01L 21/02532 Silicon, silicon germanium, germanium
• CPC Class Codes: H01L 21/02639 Preparation of substrate for selective deposition
• CPC Class Codes: H01L 21/02647 Lateral overgrowth
• CPC Class Codes: H01L 21/76224 using trench refilling with dielectric materials trench filling with polycristalline silicon H01L21/763; together with vertical isolation, e.g. trench refilling in a SOI substrate H01L21/76264
• CPC Class Codes: H01L 27/1446 in a repetitive configuration
• CPC Class Codes: H01L 27/14612 involving a transistor
• CPC Class Codes: H01L 27/14643 Photodiode arrays; MOS imagers
• CPC Class Codes: H01L 27/14689 MOS based technologies
• CPC Class Codes: H01L 31/0304 including, apart from doping materials or other impurities, only AIIIBV compounds
• CPC Class Codes: H01L 31/03046 including ternary or quaternary compounds, e.g. GaAlAs, InGaAs, InGaAsP
• CPC Class Codes: H01L 31/0312 including, apart from doping materials or other impurities, only AIVBIV compounds, e.g. SiC
• CPC Class Codes: H01L 31/103 the potential barrier being of the PN homojunction type
• CPC Class Codes: H01L 31/1037 the devices comprising active layers formed only by AIVBVI compounds
• CPC Class Codes: H01L 31/105 the potential barrier being of the PIN type
• CPC Class Codes: Y02E 10/544 Solar cells from Group III-V materials
• CPC Class Codes: Y02P 70/50 Manufacturing or production processes characterised by the final manufactured product

Abstract

Non-silicon based semiconductor devices are integrated into silicon fabrication processes by using aspect-ratio-trapping materials. Non-silicon light-sensing devices in a least a portion of a crystalline material can output electrons generated by light absorption therein. Exemplary light-sensing devices can have relatively large micron dimensions. As an exemplary application, complementary-metal-oxide-semiconductor photodetectors are formed on a silicon substrate by incorporating an aspect-ratio-trapping technique.

Claims

1. A sensor, comprising:

a substrate having first and second epitaxial crystalline structures interfacing at a coalesced portion;

a sensing region formed at or in the coalesced portion to output electrons generated by light absorption therein; and

contacts coupled to receive the electrons to obtain an output electric signal.

2. The sensor of claim 1, wherein the first or the second epitaxial crystalline structure is substantially free from dislocation defects.

3. The sensor of claim 1, wherein the first or the second epitaxial crystalline structures is comprised of a semiconductor material.

4. The sensor of claim 1, wherein the first and second epitaxial crystalline structures are disposed in first and second openings, wherein the openings are trenches formed in a crystalline substrate.

5. The sensor of claim 1, wherein the first and second epitaxial crystalline structures are disposed in first and second openings, wherein the openings are formed within a dielectric layer comprised of a dielectric material over a crystalline substrate.

6. The sensor of claim 1, wherein the sensing region comprises a p-n junction or a p-i-n structure.

7. The sensor of claim 1, wherein the sensor is a photodetector pixel of a semiconductor device;

the photodetector pixel is a complementary-metal-oxide-semiconductor photodetector; and

the photodetector comprises a p-n junction or a p-i-n structure and a metal-oxide-semiconductor transistor, wherein the p-n junction or a p-i-n structure is formed in the sensing region, and wherein the photodetector is an IR or UV detector.

8. The sensor of claim 1, wherein the coalesced portion has a width of 1 micron or larger, the width of 2 microns or larger, the width from 2 to 5 microns or the width of 5 microns or larger.

9. The sensor of claim 1, comprising:

a p-i-n structure formed within the substrate; and

an intrinsic region of the p-i-n structure is positioned to receive light in the sensing region.

10. The sensor of claim 1, wherein the first and second epitaxial crystalline structures are coalesced over an insulator configured to form at least two openings to a lattice mismatched crystalline substrate, the first and second structures in at least a portion of a corresponding one of said at least two openings.

11. The sensor of claim 10, wherein the substrate is configured with depressions in the substrate, and wherein the insulator overlies sides of the depression to form said openings and the aspect ratio of the opening is 1 or greater or the aspect ratio of the opening is 0.5 or greater, wherein the opening is a trench, recess or hole.

12. The sensor of claim 10, wherein the substrate is configured with depressions in the substrate, and wherein the insulator overlies sides of the depression to form said openings and each of said first and second epitaxial crystalline structures comprise an epitaxial lateral overgrowth (ELO) region, wherein said ELO region is at least 2 times a width of the opening, at least 5 times the width of the opening or at least 10 times the width of the openings.

13. The sensor of claim 1, wherein the first and second epitaxial crystalline materials are semiconductor materials among a group II-VI compound, a group III-V compound, group III-N compound or ternary and quaternary compounds thereof or a group IV material.

14. A method, comprising:

providing a crystalline semiconductor substrate;

forming a first trench patterned structure in the substrate;

forming a second trench patterned structure in the first trench patterned structure, wherein the second trench patterned structure has a width equal to or less than the width of the first trench patterned structure; and

forming an ART (aspect-ratio-trapping) material in the first and second trench patterned structures; and

making a photodetector formed at or in the ART material to output electrons generated by light absorption therein.

15. The method of claim 14, wherein the substrate is a silicon substrate;

and the ART material is comprised of a non-silicon semiconductor material.

16. The method of claim 14, wherein the first trench patterned structure has a width of 2 microns or larger or the width of 5 microns.

17. The method of claim 14, wherein forming the ART material comprises growing crystalline material lattice-mismatched to the crystalline substrate.

18. A semiconductor sensor, comprising:

a crystalline substrate;

an insulator having a plurality of openings to the substrate;

a crystalline material within the openings in the insulator, the crystalline material being lattice-mismatched with the substrate;

a second different buffer crystalline material being lattice-mismatched with the substrate between the substrate and the first crystalline material;

a light-sensing device in a least a portion of the crystalline material to output electrons generated by light absorption therein;

contacts coupled to receive the electrons generated by light absorption to obtain an output electric signal.

19. The sensor of claim 18, wherein the second different buffer crystalline material has a thickness over the substrate less than 100 nm, less than 60 nm, less than 40 nm, less than 20 nm or less than 10 nm.

20. The sensor of claim 18, wherein the first crystalline material comprises a group II-VI compound or ternary and quaternary compounds thereof, a group III-V compound or ternary and quaternary compounds thereof, group III-N compound or ternary and quaternary compounds thereof or a group IV material.