Method for Transistor Fabrication with Optimized Performance
First Claim
1. A CMOS semiconductor fabrication process, comprising:
- providing a first semiconductor layer;
forming NMOS and PMOS gate structures overlying the first semiconductor layer, each of the NMOS and PMOS gate structures having exposed gate sidewalls;
depositing a first contact etch stop layer over the NMOS and PMOS gate structures;
etching the first contact etch stop layer to form sidewall spacers adjacent to the NMOS and PMOS gate structures;
depositing a second contact etch stop layer over the NMOS and PMOS gate structures and the sidewall spacers;
where one of the first or second contact etch stop layers is a tensile material and the other of the first or second contact etch stop layers is a compressive or neutral material that acts as a hydrogen source.
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Accused Products
Abstract
A semiconductor process and apparatus includes forming <100> channel orientation CMOS transistors (24, 34) with enhanced hole mobility in the NMOS channel region and reduced channel defectivity in the PMOS region by depositing a first tensile etch stop layer (51) over the PMOS and NMOS gate structures, etching the tensile etch stop layer (51) to form tensile sidewall spacers (62) on the exposed gate sidewalls, and then depositing a second hydrogen rich compressive or neutral etch stop layer (72) over the NMOS and PMOS gate structures (26, 36) and the tensile sidewall spacers (62). In other embodiments, a first hydrogen-rich etch stop layer (81) is deposited and etched to form sidewall spacers (92) on the exposed gate sidewalls, and then a second tensile etch stop layer (94) is deposited over the NMOS and PMOS gate structures (26, 36) and the sidewall spacers (92).
21 Citations
20 Claims
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1. A CMOS semiconductor fabrication process, comprising:
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providing a first semiconductor layer; forming NMOS and PMOS gate structures overlying the first semiconductor layer, each of the NMOS and PMOS gate structures having exposed gate sidewalls; depositing a first contact etch stop layer over the NMOS and PMOS gate structures; etching the first contact etch stop layer to form sidewall spacers adjacent to the NMOS and PMOS gate structures; depositing a second contact etch stop layer over the NMOS and PMOS gate structures and the sidewall spacers; where one of the first or second contact etch stop layers is a tensile material and the other of the first or second contact etch stop layers is a compressive or neutral material that acts as a hydrogen source. - View Dependent Claims (2, 3, 4, 5, 6, 8, 9, 10)
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7. The process of claim 7, where depositing the second contact etch stop layer comprises depositing a tensile contact etch stop layer over the NMOS and PMOS gate structures and the sidewall spacers.
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11. A CMOS fabrication process for forming a semiconductor integrated circuit, comprising:
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providing a first semiconductor layer having a <
100>
channel orientation,forming PMOS and NMOS gate structures over the first semiconductor layer, where the PMOS and NMOS gate structures comprise implant spacers formed on sidewalls of the PMOS and NMOS gate structures; removing the implant spacers from the sidewalls of the PMOS and NMOS gate structures; forming sidewall spacers adjacent to the PMOS and NMOS gate structures; and forming an etch stop layer over the sidewall spacers and the PMOS and NMOS gate structures; where one of the sidewall spacers or the etch stop layer is formed with a tensile material and the other of the sidewall spacers or the etch stop layer is formed with a hydrogen-rich material. - View Dependent Claims (12, 13, 14, 15, 16, 17, 18)
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19. A semiconductor device comprising:
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a semiconductor substrate having a <
100>
channel orientation;PMOS and NMOS gate structures overlying the silicon substrate; first spacer structures formed adjacent to the PMOS and NMOS gate structures after source/drain implantation; and a contact etch stop layer formed over the PMOS and NMOS gate structures and the first spacer structures; where either the first spacer structures or the contact etch stop layer is formed with a tensile material that stresses channel regions formed below the NMOS gate structures, and the other of the first spacer structures or the contact etch stop layer is formed with a hydrogen-rich material that introduces hydrogen to passivate dangling bonds in channel semiconductor regions below the PMOS gate structures. - View Dependent Claims (20)
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Specification