SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF

• US 20100078707A1
• Filed: 09/30/2008
• Published: 04/01/2010
• Est. Priority Date: 09/30/2008
• Status: Active Grant

• Current Assignee: Infineon Technologies Austria Ag (Infineon Technologies AG)
• Original Assignee: Infineon Technologies Austria Ag (Infineon Technologies AG)
• Inventors: Hirler, Franz, Rieger, Walter, Haeberlen, Oliver, Krumrey, Joachim
• Granted Patent: US 8,022,474 B2
• Time in Patent Office: Days
• US Class Current: 257/328
• CPC Class Codes: H01L 21/26586 characterised by the angle between the ion beam and the crystal planes or the main crystal surface
• CPC Class Codes: H01L 27/0629 in combination with diodes, or resistors, or capacitors
• CPC Class Codes: H01L 29/0623 Buried supplementary region, e.g. buried guard ring multi-RESURF H01L29/0634
• CPC Class Codes: H01L 29/0834 Anode regions of thyristors or gated bipolar-mode devices, e.g. supplementary regions surrounding anode regions
• CPC Class Codes: H01L 29/086 Impurity concentration or distribution
• CPC Class Codes: H01L 29/0878 Impurity concentration or distribution
• CPC Class Codes: H01L 29/1095 Body region, i.e. base region, of DMOS transistors or IGBTs cell layout H01L29/0696
• CPC Class Codes: H01L 29/404 Multiple field plate structures
• CPC Class Codes: H01L 29/407 Recessed field plates, e.g. trench field plates, buried field plates
• CPC Class Codes: H01L 29/41766 with at least part of the source or drain electrode having contact below the semiconductor surface, e.g. the source or drain electrode formed at least partially in a groove or with inclusions of conductor inside the semiconductor H01L29/41733 - H01L29/41758 take precedence
• CPC Class Codes: H01L 29/42368 the thickness being non-uniform
• CPC Class Codes: H01L 29/495 the conductor material next to the insulator being a simple metal, e.g. W, Mo H01L29/4908, H01L29/4983 take precedence
• CPC Class Codes: H01L 29/4966 the conductor material next to the insulator being a composite material, e.g. organic material, TiN, MoSi2 H01L29/4908, H01L29/4983 take precedence
• CPC Class Codes: H01L 29/66727 with a step of recessing the source electrode
• CPC Class Codes: H01L 29/66734 with a step of recessing the gate electrode, e.g. to form a trench gate electrode
• CPC Class Codes: H01L 29/7397 and a gate structure lying on a slanted or vertical surface or formed in a groove, e.g. trench gate IGBT
• CPC Class Codes: H01L 29/7803 structurally associated with at least one other device assemblies H01L25/00; integrated circuits H01L27/00
• CPC Class Codes: H01L 29/7805 in antiparallel, e.g. freewheel diode
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236

Abstract

A semiconductor device includes a source metallization, a source region of a first conductivity type in contact with the source metallization, a body region of a second conductivity type which is adjacent to the source region. The semiconductor device further includes a first field-effect structure including a first insulated gate electrode and a second field-effect structure including a second insulated gate electrode which is electrically connected to the source metallization. The capacitance per unit area between the second insulated gate electrode and the body region is larger than the capacitance per unit area between the first insulated gate electrode and the body region.

Claims

1. A semiconductor device, comprising:

a source metallization;

a first field-effect structure including a source region of a first conductivity type, the source region being electrically connected to the source metallization;

a body region of a second conductivity type adjacent to the source region;

a first gate electrode and a first insulating region which is arranged at least between the first gate electrode and the body region, the first gate electrode, the first insulating region and the body region forming a first capacitance, the first capacitance having a first capacitance per unit area;

a second field-effect structure including a source region of the first conductivity type;

a body region of the second conductivity type adjacent to the source region;

a second gate electrode and a second insulating region which is arranged at least between the second gate electrode and the body region, the source region and the second gate electrode being electrically connected to the source metallization;

the second gate electrode, the second insulating region and the body region forming a second capacitance, the second capacitance having a second capacitance per unit area; and

the second capacitance per unit area being larger than the first capacitance per unit area.

2. The semiconductor device of claim 1, wherein the first insulating region has a first thickness d₁ between the first gate electrode and the body region;

wherein the second insulating region has a second thickness d₂ between the second gate electrode and the body region; and

wherein the second thickness d₂ is smaller than the first thickness d₁.

3. The semiconductor device of claim 1, wherein the second capacitance per unit area is larger than about 4.3 nF/mm².

4. The semiconductor device of claim 1, wherein the first insulating region has a first permittivity and wherein the second insulating region has a second permittivity which is higher than the first permittivity.

5. The semiconductor device of claim 1, wherein the semiconductor device is selected from a group consisting of a lateral MOSFET, a UMOSFET, a DMOSFET, a Superjunction-MOSFET or an reverse conducting IGBT.

6. The semiconductor device of claim 1, further comprising a common drift region of the first conductivity type;

the common drift region forming a pn-junction with both body regions;

wherein the body region of the first field effect structure and the common drift region form a body diode;

wherein the second field effect structure forms a MOS-gated diode (MGD) connected in parallel to the body diode;

wherein the total current through the semiconductor device in forward biasing of the body diode is dominated by an unipolar current above an average current flow density in the drift region; and

wherein the average current flow density is about 1 mA/mm².

7. The semiconductor device of claim 6, wherein the MOS-controlled diode has a threshold voltage which depends on the current per channel width, wherein the threshold voltage is lower than about 0.26 V for a current per channel width of 10 mA/m.

8. The semiconductor device of claim 1, comprising a plurality of first field-effect structures and second field-effect structures, wherein at least a part of the plurality of first field-effect structures and second field-effect structures are arranged in a regular pattern.

9. The semiconductor device of claim 8, wherein, in the regular pattern, the ratio between the first field-effect structures and the second field-effect structures is in a range between about 1:

1 to 100;

1.

10. The semiconductor device of claim 1, wherein the body region includes a first body sub-region adjoining the first insulating region and a second body sub-region adjoining the second insulating region, wherein the doping concentration of the second body sub-region is lower than the doping concentration of the first body sub-region.

11. The semiconductor device of claim 1, wherein at least one of the first and the second field-effect structures further includes at least one field plate electrically connected to the source metallization.

12. The semiconductor device of claim 1, wherein the first gate electrode includes a material having a first workfunction, and wherein the second gate electrode includes a material having a second workfunction which is smaller than the first work function.

13. A power semiconductor device, comprising:

a source metallization;

a source region of a first conductivity type, the source region being connected to the source metallization;

a body region of a second conductivity type adjacent to the source region;

a drift region of a first conductivity type adjacent to the body region;

a third conductive region of a second conductivity type buried within the drift region; and

a trench extending from the source region through the body region and at least partially into the drift region;

the trench adjoining the third conductive region and including a conductive plug and an insulating layer, which insulates the conductive plug from the body region, the conductive plug forming an Ohmic connection between the source metallization and the third conductive region;

the conductive plug, the insulating layer and the body region forming a field effect structure having a gate capacitance per unit area.

14. The semiconductor device of claim 13, wherein the body region is electrically connected to the source metallization.

15. The semiconductor device of claim 13, further comprising a further field-effect structure having a gate capacitance per unit area.

16. The semiconductor device of claim 15, wherein the capacitance per unit area of the field effect structure is higher than the gate capacitance per unit area of the further field effect structure.

17. A semiconductor device, comprising:

a source metallization;

a gate metallization;

a drift region of a first conductivity type;

a first and a second source region of the first conductivity type electrically connected to the source metallization;

a body region of a second conductivity type arranged between the source regions and the drift region;

a first trench extending from the first source region through the body region at least partially into the drift region, the first trench including a first conductive region forming a first gate electrode electrically connected to the gate metallization, and a first insulating region which is arranged at least between the first conductive region and the body region, wherein the first conductive region, the first insulating region and the body region form a first capacitance having a first capacitance per unit area;

—

a second trench extending from the second source region through the body region at least partially into the drift region, the second trench including a second conductive region forming a second gate electrode electrically connected to the source metallization; and

a second insulating region which is arranged at least between the first conductive region and the body region, wherein the second conductive region, the second insulating region and the body region form a second capacitance having a second capacitance per unit area; and

the second capacitance per unit area being larger than the first capacitance per unit area.

18. The semiconductor device of claim 17, wherein the body region includes a first inversion channel region along the first insulating region, the first inversion channel region having a first channel length extending from the first source region to the drift region;

wherein the body region includes a second inversion channel region along the second insulating region, the second inversion channel region having a second channel length extending from the second source region to the drift region; and

wherein the second channel length is smaller than the first channel length.

19. The semiconductor device of claim 17, wherein the first conductive region extends in the first trench up to a first depth, wherein the second conductive region extends in the second trench up to a second depth, and wherein the first depth is larger than the second depth.

20. A method for forming a semiconductor device, comprising:

providing a semiconductor body of a first conductivity type;

forming a first field-effect structure including a source region of the first conductivity type;

a body region of a second conductivity type which is adjacent to the source region;

a first gate electrode and a first insulating region which is arranged at least between the first gate electrode and the body region such that the first gate electrode, the first insulating region and the body region form a first capacitance, the first capacitance having a first capacitance per unit area;

forming a second field-effect structure including a source region of the first conductivity type;

a body region of a second conductivity type which is adjacent to the source region;

a second gate electrode and a second insulating region which is arranged at least between the second gate electrode and the body region such that the second gate electrode, the second insulating region and the body region form a second capacitance, the second capacitance having a second capacitance per unit area; and

forming a source metallization at least in electrical contact to the source regions of the first and second field-effect structures and the second gate electrode;

the first and second field-effect structures being formed such that the second capacitance per unit area is higher than the first capacitance per unit area.

21. A method for forming a semiconductor device, comprising:

providing a semiconductor substrate of a first conductivity type;

forming a first trench and a second trench in the semiconductor substrate;

forming a first oxide layer covering at least a lower portion of the walls of the first trench and a lower portion of the walls of the second trench;

forming a conductive region at least in the lower portion of the first trench and at least in the lower portion of the second trench;

forming a protecting region on the second trench;

performing a thermal oxidation process to form a first insulating region on the side walls in an upper portion of the first trench, wherein the second trench is protected during the thermal oxidation by the protecting region such that the semiconductor substrate forming the walls of the second trench is not oxidized;

forming a second insulating region on the side walls in an upper portion of the second trench;

forming a first gate electrode in the upper portion of the first trench and a second gate electrode in the upper portion of the second trench;

forming source regions of the first conductivity type and a body region of a second conductivity type adjacent to the source regions; and

forming a source metallization in electrical contact to the source regions and the second gate electrode.

22. The method of claim 21, wherein the first insulating region and the second insulating region are formed such that a capacitance per unit area between the second gate electrode and the body region is higher than a capacitance per unit area between the first gate electrode and the body region.

23. The method of claim 21, wherein the process of forming a protecting region includes forming the protecting region at least on the side walls of the upper portion of the second trench prior to performing the thermal oxidation process.

24. The method of claim 21, wherein the process of forming a protecting region includes complete filling of the second trench with the first oxide layer and the conductive region during the thermal oxidation process.

25. The method of claim 21, further comprising:

masking the first trench; and

subsequently

performing an etching process to expose the upper portion of the second trench.