High-voltage metal oxide semiconductor device and fabrication method thereof

• US 20100078737A1
• Filed: 09/30/2008
• Published: 04/01/2010
• Est. Priority Date: 09/30/2008
• Status: Active Grant

• Current Assignee: Niko Semiconductor Co., Ltd
• Original Assignee: Niko Semiconductor Co., Ltd
• Inventors: Tu, Kao-Way
• Granted Patent: US 8,222,689 B2
• Time in Patent Office: Days
• US Class Current: 257/409
• CPC Class Codes: H01L 29/0619 with a supplementary region doped oppositely to or in rectifying contact with the semiconductor containing or contacting region, e.g. guard rings with PN or Schottky junction
• CPC Class Codes: H01L 29/0623 Buried supplementary region, e.g. buried guard ring multi-RESURF H01L29/0634
• CPC Class Codes: H01L 29/0634 Multiple reduced surface field (multi-RESURF) structures, e.g. double RESURF, charge compensation, cool, superjunction (SJ), 3D-RESURF, composite buffer (CB) structures
• CPC Class Codes: H01L 29/407 Recessed field plates, e.g. trench field plates, buried field plates
• CPC Class Codes: H01L 29/42376 characterised by the length or the sectional shape
• CPC Class Codes: H01L 29/66734 with a step of recessing the gate electrode, e.g. to form a trench gate electrode
• CPC Class Codes: H01L 29/7802 Vertical DMOS transistors, i.e. VDMOS transistors
• CPC Class Codes: H01L 29/7808 the other device being a breakdown diode, e.g. Zener diode
• CPC Class Codes: H01L 29/7811 with an edge termination structure guard regions per se H01L29/0619; field plates per se H01L29/402
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236

Abstract

A high-voltage metal oxide semiconductor device comprising a main body of a first conductivity type, a conductive structure, a first well of a second conductivity type, a source region of the first conductivity type, and a second well of the second conductivity type is provided. The conductive structure has a first portion and a second portion. The first portion is extended from an upper surface of the main body into the main body. The second portion is extended along the upper surface of the main body. The first well is located in the main body and below the second portion. The first well is kept away from the first portion with a predetermined distance. The source region is located in the first well. The second well is located in the main body and extends from a bottom of the first portion to a place close to a drain region.

Claims

1. A high-voltage metal oxide semiconductor device comprising:

a main body of a first conductivity type;

a conductive structure, having a first portion and a second portion, the first portion extending from an upper surface of the main body into the main body, and the second portion extending along the upper surface of the main body;

a first well of a second conductivity type, located in the main body below the second portion, and kept away from the first portion with a predetermined distance;

a source region of the first conductivity type, located in the first well; and

a second Well of the second conductivity type, located in the main body and extending from a bottom of the first portion to a place close to a drain region.

2. The high-voltage metal oxide semiconductor device as claimed in claim 1, wherein the first portion is connected to the second portion, and the conductive structure is electrically connected to a gate electrode.

3. The high-voltage metal oxide semiconductor device as claimed in claim 1, wherein a dielectric layer is interposed between the first portion and the second portion, the first portion is electrically connected to the source region, and the second portion is electrically connected to a gate electrode.

4. The high-voltage metal oxide semiconductor device as claimed in claim 1, wherein a length of the first portion of the conductive structure is greater than a depth of the first well.

5. The high-voltage metal oxide semiconductor device as claimed in claim 1, wherein the drain region is located on a bottom of the main body.

6. The high-voltage metal oxide semiconductor device as claimed in claim 1, wherein the second well and the first portion are separated by at least an oxide layer and a potential of the second well depends on a potential of the first portion of the conductive structure.

7. The high-voltage metal oxide semiconductor device as claimed in claim 1, wherein a width of the second well is greater than a width of the first portion.

8. A high-voltage metal oxide semiconductor device comprising:

a main body of a first conductivity type;

a gate conductive layer, extended along an upper surface of the main body;

two first wells of a second conductivity type, located in the main body corresponding to two opposite edges of the gate conductive layer;

two source regions of the first conductivity type, located in the two first wells respectively and beneath the two opposite edges of the gate conductive layer; and

a second well of the second conductivity type, which is located in the main body and extended beneath the gate conductive layer to a place close to a substrate, being electrically connected to a gate electrode or a source electrode and away from the two first wells with a predetermined distance, and a distance between the second well and the gate conductive layer being greater than depth of the first well.

9. The high-voltage metal oxide semiconductor device as claimed in claim 8, further comprising a guard ring of the second conductivity type, located in the main body and surrounding the first wells, a depth of the guard ring being greater than that of the depth of the first well, and a lower edge of the guard ring being connected to the second well.

10. The high-voltage metal oxide semiconductor device as claimed in claim 9, wherein the guard ring is electrically connected to the source electrode through a source metal layer.

11. The high-voltage metal oxide semiconductor device as claimed in claim 9, wherein the guard ring is electrically connected to the gate electrode through the gate conductive layer.

12. A fabrication method of a high-voltage metal oxide semiconductor comprising the steps of:

(a) providing a substrate;

(b) forming a first epitaxial layer of a first conductivity type on the substrate;

(c) defining a doping region in the first epitaxial layer by using a mask and implanting dopants of a second conductivity type in the first epitaxial layer to form a first doped region;

(d) repeating steps (b) and (c) more than once;

(e) forming a second epitaxial layer of the first conductivity type on the first epitaxial layers;

(f) forming a trench exposing the uppermost first doped region;

(g) forming a conductive structure with a first portion and a second portion on the second epitaxial layer, the first portion located in the trench, and the second portion extended along an upper surface of the second epitaxial layer;

(h) implanting dopants of the second conductivity type in the second epitaxial layer to form a plurality of first wells, which is away from the first portion with a predetermined distance; and

(i) forming a plurality of source regions of the first conductivity type in the first wells.

13. The fabrication method as claimed in claim 12, wherein the step of forming the conductive structure comprising:

forming a first oxide layer covering the second epitaxial layer;

depositing a polysilicon layer; and

defining location of the conductive structure by using a gate mask and removing unwanted portion of the polysilicon layer.

14. The fabrication method as claimed in claim 12, wherein the step of forming the conductive structure comprising:

forming a first oxide layer covering the second epitaxial layer;

depositing a first polysilicon layer;

etching back the first polysilicon layer to form the first portion;

forming a second oxide layer covering exposed surface of the first portion;

depositing a second polysilicon layer; and

defining location of the second portion by using a gate mask and removing unwanted portion of the second polysilicon layer.

15. The fabrication method as claimed in claim 14, further comprising the step of electrically connecting the first portion to the source region.

16. The fabrication method as claimed in claim 15, further comprising:

depositing a dielectric layer and forming a plurality of contact windows and an opening in the dielectric layer, wherein the contact windows is used to expose the source regions and the first wells under the dielectric layer, and the opening is used to expose the first portion; and

forming a source metal connected to the source regions and the first portion through the contact windows and the opening respectively.

17. The fabrication method as claimed in claim 12, wherein the first doped regions are expanded by heat and mutually connected to form a vertical well.

18. The fabrication method as claimed in claim 17, wherein the vertical well and the substrate are separated by a doped region of the first conductivity type.

19. The fabrication method of claim 12, wherein a width of the first doped region is greater than that of the trench.

20. A fabrication method of a high-voltage metal oxide semiconductor comprising the steps of:

(a) providing a substrate;

(b) forming a first epitaxial layer of a first conductivity type on the substrate;

(c) defining a doping region in the first epitaxial layer by using a mask and implanting dopants of a second conductivity type in the first epitaxial layer to form a first doped region;

(d) repeating steps (b) and (c) more than once;

(e) forming a second epitaxial layer of the first conductivity type on the first epitaxial layers, wherein the first doped regions are expanded by heat and mutually connected to form a vertical well;

(f) forming a guard ring of the second conductivity type in the second epitaxial layer to define an active region, and the guard ring being planarly overlapped with the vertical well;

(g) forming a gate conductive layer on an upper surface of the second epitaxial layer and aligned to the vertical well;

(h) implanting dopants of the second conductivity type in the second epitaxial layer by using the gate conductive layer as a mask and driving in the dopants,to form a plurality of first wells away from the vertical well with a predetermined distance, and the guard ring being expanded downward to connect the vertical well; and

(i) forming a plurality of source regions of the first conductivity type in the first wells.

21. The fabrication method as claimed in claim 20, wherein the gate conductive layer formed on the upper surface of the second epitaxial layer is extended along the second epitaxial layer and connected to the guard ring.

22. The fabrication method as claimed in claim 20, further comprising the step of forming a source metal layer on the dielectric layer to connect the guard ring and the source regions.

23. The fabrication method as claimed in claim 20, wherein the vertical well is away from the substrate with a predetermined space.