On-Chip Radio Frequency Shield with Interconnect Metallization

• US 20100078777A1
• Filed: 09/30/2008
• Published: 04/01/2010
• Est. Priority Date: 09/30/2008
• Status: Active Grant

• Current Assignee: Infineon Technologies AG
• Original Assignee: Infineon Technologies AG
• Inventors: Meyer, Thorsten, Brunnbauer, Markus, Barth, Hans-Joachim, Koerner, Heinrich
• Granted Patent: US 8,063,469 B2
• Time in Patent Office: Days
• US Class Current: 257/659
• CPC Class Codes: H01L 2224/13099 Material
• CPC Class Codes: H01L 23/481 Internal lead connections, e.g. via connections, feedthrough structures
• CPC Class Codes: H01L 23/5225 Shielding layers formed together with wiring layers
• CPC Class Codes: H01L 23/552 Protection against radiation, e.g. light or electromagnetic waves
• CPC Class Codes: H01L 23/585 comprising conductive layers or plates or strips or rods or rings H01L23/60, H01L23/62, H01L23/64, H01L23/66 take precedence
• CPC Class Codes: H01L 23/66 High-frequency adaptations
• CPC Class Codes: H01L 2924/00014 the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details

Abstract

Structure and method for fabricating a system on chip with an on-chip RF shield including interconnect metallization is described. In one embodiment, the system on chip includes an RF circuitry disposed on a first portion of a top surface of a substrate, and a semiconductor circuitry disposed on a second portion of the top surface of the substrate. An interconnect RF barrier is disposed between the RF circuitry and the semiconductor circuitry, the interconnect RF barrier coupled to a ground potential node.

Claims

1. A semiconductor chip comprising:

a first semiconductor circuitry including an RF circuit disposed on a first portion of a top surface of a substrate; and

a crack stop adjacent the first semiconductor circuitry, the crack stop disposed along an edge of the system on chip, wherein the crack stop is coupled to a ground potential.

2. The semiconductor chip of claim 1 further comprising:

a second semiconductor circuitry disposed on a second portion of the top surface of the substrate; and

an interconnect radio frequency (RF) barrier disposed between the first semiconductor circuitry and the second semiconductor circuitry, the interconnect RF barrier coupled to the ground potential.

3. The semiconductor chip of claim 2, wherein the second semiconductor circuitry comprises no RF devices.

4. The semiconductor chip of claim 3, wherein the interconnect RF barrier comprises:

a vertical section comprising metal lines and vias, the vertical section disposed above a region of the substrate comprising no active devices; and

a horizontal section comprising metal lines, the horizontal section disposed at least partially over the first semiconductor circuitry.

5. The semiconductor chip of claim 4, wherein the vertical section is coupled to a through substrate via disposed in the substrate.

6. The semiconductor chip of claim 4, wherein the vias comprise line segments.

7. The semiconductor chip of claim 4, wherein the metal lines are arranged in multiple rows around the first semiconductor circuitry.

8. The semiconductor chip of claim 7, wherein the metal lines are staggered between the multiple rows.

9. The semiconductor chip of claim 2, wherein the interconnect RF barrier includes openings for interconnects between the first semiconductor circuitry and the second semiconductor circuitry.

10. The semiconductor chip of claim 1, further comprising a moisture barrier adjacent the first semiconductor circuitry, the moisture barrier disposed along an edge of the system on chip, wherein the moisture barrier is coupled to a ground potential node.

11. The semiconductor chip of claim 1, further comprising a through substrate via disposed under the crack stop, wherein the crack stop is coupled to the through substrate via.

12. A semiconductor chip comprising:

first semiconductor circuitry disposed on a first portion of a top surface of a substrate; and

a first conductive structure adjacent the first semiconductor circuitry, the first conductive structure disposed along an edge of the system on chip, wherein the first conductive structure is designed to block transmission of electromagnetic waves from and to the first semiconductor circuitry, wherein the first conductive structure comprises a crack stop or a moisture barrier.

13. The semiconductor chip of claim 12, further comprising a through substrate via disposed under the first conductive structure, wherein the first conductive structure is coupled to the through substrate via.

14. The semiconductor chip of claim 12, further comprising a second conductive structure adjacent the first semiconductor circuitry, the second conductive structure disposed along an edge of the system on chip, wherein the second conductive structure is designed to block transmission of electromagnetic waves from and to the first semiconductor circuitry, wherein the second conductive structure comprises a crack stop or a moisture barrier, and wherein the first and the second conductive structures are different structures.

15. The semiconductor chip of claim 12, further comprising:

a second semiconductor circuitry disposed on a second portion of the top surface of the substrate; and

an interconnect radio frequency (RF) barrier disposed between the first semiconductor circuitry and the second semiconductor circuitry, wherein the interconnect RF barrier blocks transmission of electromagnetic waves between the first and the second semiconductor circuitry.

16. A semiconductor chip comprising:

a moisture barrier disposed around a substrate, wherein the moisture barrier is coupled to a ground potential node; and

a first semiconductor circuit disposed at a surface of the substrate adjacent the moisture barrier, wherein the first semiconductor circuit comprises a radio frequency (RF) circuit.

17. The semiconductor chip of claim 16 further comprising:

a second semiconductor circuit disposed adjacent the RF circuit, the second semiconductor circuit including no RF circuitry; and

an interconnect RF barrier disposed between the first semiconductor circuit and the second semiconductor circuit, the interconnect RF barrier comprising metal lines and vias, wherein the interconnect RF barrier is disposed above a part of the substrate comprising no active devices, and wherein the interconnect RF barrier is coupled to the ground potential.

18. The semiconductor chip of claim 17, wherein the interconnect RF barrier is coupled to a through substrate via disposed in the substrate.

19. The semiconductor chip of claim 17, wherein the interconnect RF barrier comprises a vertical section comprising metal lines and vias.

20. The semiconductor chip of claim 17, further comprising a top shield comprising metal lines disposed on a top most level of metallization, the top shield coupled to the interconnect RF barrier and disposed at least partially over the RF circuit.

21. The semiconductor chip of claim 17, further comprising a through substrate via coupled to the moisture barrier, the through substrate via disposed under the moisture barrier.

22. The semiconductor chip of claim 17, wherein the interconnect RF barrier shields the second semiconductor circuit from electromagnetic radiation emanating from the first semiconductor circuit.

23. A system on chip comprising:

a conductive structure surrounding a substrate, wherein no active circuitry is disposed between the conductive structure and an edge of the substrate;

RF circuitry disposed in a first portion of the substrate;

semiconductor circuitry disposed in a second portion of the substrate, the semiconductor circuitry including no RF circuitry; and

an interconnect RF barrier disposed between the first portion of the substrate and the second portion of the substrate and above a part of the substrate comprising no active devices, the interconnect RF barrier comprising metal lines and vias, wherein the interconnect RF barrier and the conductive structure are designed to substantially block electromagnetic radiation entering or radiating from the RF circuitry.

24. The system on chip of claim 23, wherein the conductive structure and the interconnect RF barrier surround substantially all of the RF circuitry.

25. The system on chip of claim 23, wherein the conductive structure comprises a crack stop and/or a moisture barrier.

26. A method of fabricating a system on chip, the method comprising:

forming RF circuitry and non-RF circuitry in an active region of a substrate;

forming through substrate vias in the substrate between the RF circuitry and the non-RF circuitry, wherein forming the through substrate vias comprises filling deep openings in the substrate with a conductive material;

after forming the through substrate vias, forming a stack of metal lines and vias disposed on the through substrate via, the last metal line of the stack at least partially disposed over the RF circuitry; and

coupling the stack of metal lines and vias and the through substrate via to a ground potential node.

27. The method of claim 26, wherein the substrate vias and the stack of metal lines are formed between the RF circuitry and an edge of the substrate.

28. The method of claim 26, wherein the stack of metal lines and vias and the last metal line form an interconnect RF barrier that shields the semiconductor circuitry from electromagnetic radiation emanating from the RF circuitry.

29. The method of claim 26, further comprising thinning the substrate to expose the through substrate vias from the back side after forming the stack of metal lines and vias.

30. The method of claim 26, wherein forming the through substrate vias comprises forming through substrate vias spaced apart by a distance less than about 300 um.