SEMICONDUCTOR APPARATUS, SUBSTRATE DESIGN METHOD, AND SUBSTRATE DESIGN APPARATUS

• US 20100078810A1
• Filed: 09/28/2009
• Published: 04/01/2010
• Est. Priority Date: 09/30/2008
• Status: Active Grant

• Current Assignee: Fujitsu Limited
• Original Assignee: Fujitsu Limited
• Inventors: Sakai, Hidehisa, Matsui, Noriyuki
• Granted Patent: US 8,816,510 B2
• Time in Patent Office: Days
• US Class Current: 257/737
• CPC Class Codes: H01L 23/3677 Wire-like or pin-like cooling fins or heat sinks
• CPC Class Codes: H01L 23/49816 Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
• CPC Class Codes: H01L 23/49827 Via connections through the substrates, e.g. pins going through the substrate, coaxial cables H01L23/49822, H01L23/49833, H01L23/4985, H01L23/49861 take precedence
• CPC Class Codes: H01L 23/49838 Geometry or layout
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
• CPC Class Codes: H01L 2924/15311 being a ball array, e.g. BGA

Abstract

A semiconductor apparatus including: a substrate; and a semiconductor chip mounted on the substrate, wherein the substrate has plural holes, and the plural holes are provided such that the density on a substrate surface of the holes in a first area, which is an area of the substrate facing a semiconductor chip peripheral portion, is higher than the density on the substrate surface of the holes in an area excluding the first area on the substrate.

Claims

1. A semiconductor apparatus comprising:

a substrate; and

a semiconductor chip mounted on the substrate, wherein the substrate has plural holes, and the plural holes are provided such that the density on a substrate surface of the holes in a first area, which is an area of the substrate facing a semiconductor chip peripheral portion, is higher than the density on the substrate surface of the holes in an area excluding the first area on the substrate.

2. The semiconductor apparatus according to claim 1, wherein the semiconductor chip has plural signal terminals, and the substrate has a first surface, which is a surface on which the semiconductor chip is mounted and has plural first electrodes to be connected to the signal terminals, a second surface, which is the back surface of the first surface and has plural second electrodes connectable to an external substrate, and plural wires that connect the first electrodes and the second electrodes through the holes.

3. The semiconductor apparatus according to claim 2, wherein, on the substrate, a first boundary, which is a boundary of the area facing the semiconductor chip, is a square.

4. The semiconductor apparatus according to claim 3, wherein the first area is an area which is the inside of the first boundary and has a distance equal to or shorter than a predetermined first distance from the first boundary.

5. The semiconductor apparatus according to claim 4, wherein the first distance is a minimum distance between the second electrodes.

6. The semiconductor apparatus according to claim 4, wherein the holes in the first area are provided at the positions at an equal distance from two, which are neighboring each other, of the second electrodes.

7. The semiconductor apparatus according to claim 4, wherein the density on the substrate surface of the holes in a second area, which is an area within the first area and has a distance equal to or shorter than a predetermined second distance from two sides, which are neighboring each other, of the first boundary is higher than the density on the substrate surface of the holes provided in the area excluding the second area in the first area.

8. The semiconductor apparatus according to claim 7, wherein the second distance is a minimum distance between the second electrodes.

9. The semiconductor apparatus according to claim 3, wherein the first area is an area between a second boundary, which is an innermost square of the squares formed by connecting the centers of the second electrodes outside of the first boundary and a third boundary, which is an outermost square of the squares formed by connecting the centers of the second electrodes inside of the first boundary.

10. The semiconductor apparatus according to claim 9, wherein the holes in the first area are provided at the positions at an equal distance from four, which are neighboring each other, of the second electrodes.

11. The semiconductor apparatus according to claim 2, wherein the wires extend through the holes in the first area.

12. The semiconductor apparatus according to claim 2, wherein the holes in the first area extend between the first surface and the second surface.

13. The semiconductor apparatus according to claim 2, wherein:

the substrate is a multi-layered substrate; and

the holes in the first area have openings of the holes on the first surface or the second surface.

14. The semiconductor apparatus according to claim 2, wherein the first area is an area within the substrate surface and has a distance equal to or shorter than a predetermined first distance from the first boundary.

15. A substrate design method that designs a substrate for a semiconductor apparatus having a substrate and a semiconductor chip mounted on the substrate, the substrate being connectable to an external substrate, the method comprising:

determining the position of the semiconductor chip on the substrate;

determining the positions of the plural holes on the substrate on the basis of the determined position of the semiconductor chip; and

determining the positions of the plural holes such that the density on a substrate surface of the holes in a first area, which is an area of the substrate facing a semiconductor chip peripheral portion, is higher than the density on the substrate surface of the holes in an area excluding the first area on the substrate.

16. The substrate design method according to claim 15, in which:

the semiconductor chip has plural signal terminals;

the substrate has a first surface, which is a surface on which the semiconductor chip is mounted and has plural first electrodes to be connected to the signal terminals, a second surface, which is the back surface of the first surface and has plural second electrodes connectable to an external substrate, the method further comprising;

determining the positions of wires that connect the first electrodes and the second electrodes through a part of the holes the positions of which have been determined.

17. The substrate design method according to claim 16, wherein, on the substrate, a first boundary, which is a boundary of the area facing the semiconductor chip, is a square.

18. The substrate design method according to claim 17, wherein the first area is an area which is the inside of the first boundary and having a distance equal to or shorter than a predetermined first distance from the first boundary.

19. The substrate design method according to claim 15, wherein the positions of the wires are determined such that the wires is extendable through the holes within the first area.

20. A substrate design apparatus that designs a substrate for a semiconductor apparatus having a substrate and a semiconductor chip mounted on the substrate, the substrate being connectable to an external substrate, the substrate design apparatus comprising:

a semiconductor chip position determining section that determines the position of the semiconductor chip on the substrate, determines the positions of the plural holes on the substrate on the basis of the position of the semiconductor chip, which is determined by the semiconductor chip position determining section; and

a hole position determining section that determines the positions of the plural holes such that the density on a substrate surface of the holes in a first area, which is an area of the substrate facing a semiconductor chip peripheral portion, is higher than the density on the substrate surface of the holes in an area excluding the first area on the substrate.