CMOS IMAGER AND SYSTEM WITH SELECTIVELY SILICIDED GATES
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Abstract
The invention also relates to an apparatus and method for selectively providing a silicide coating over the transistor gates of a CMOS imager to improve the speed of the transistor gates. The method further includes an apparatus and method for forming a self aligned photo shield over the CMOS imager.
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Citations
111 Claims
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1-86. -86. (canceled)
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87. A CMOS imager, comprising:
an array of pixels, at least one pixel comprising; a photo-collection region to accumulate photo-generated charge, wherein silicide is substantially absent from a surface of the photo-collection region; and a transfer transistor to transfer the charge from the photo-collection region to a storage node, wherein the transfer transistor includes a polysilicon transfer gate comprising silicide and the storage node is substantially free of silicide. - View Dependent Claims (88, 89, 90, 91, 92, 93, 94, 95, 96, 97, 98, 99, 100, 101, 102)
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103. A camera system, comprising:
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a bus; a processor; random access memory coupled to the processor via the bus; a CMOS imager coupled to the processor via the bus, the imager comprising an array of pixels, each pixel containing silicided transistor gates, transistor source/drain regions free from silicide, a photodiode, and shallow trench isolation, the imager configured to perform correlated sampling of each pixel, analog-to-digital conversion of the output of each pixel, and image processing.
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104. A camera system, comprising:
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a processor; random access memory coupled to the processor; a non-volatile memory subsystem coupled to the processor and configured to enable use of removable storage media; and a CMOS imager, coupled to the processor, comprising a pixel array having silicided gates of transistors, unsilicided source/drain regions of the transistors, and an analog-to-digital converter. - View Dependent Claims (105, 106, 107, 108, 109, 110, 111)
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Specification