SEMICONDUCTOR LIGHT EMITTING DEVICE HAVING TEXTURED STRUCTURE AND METHOD OF MANUFACTURING THE SAME

• US 20100081221A1
• Filed: 12/04/2009
• Published: 04/01/2010
• Est. Priority Date: 12/08/2004
• Status: Active Grant

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Samsung Electro-Mechanics Co., Ltd. (Samsung Group)
• Inventors: LEE, Jeong-wook, Sung, Youn-joon, Paek, Ho-sun
• Granted Patent: US 8,114,691 B2
• Time in Patent Office: Days
• US Class Current: 438/29
• CPC Class Codes: H01L 33/007 comprising nitride compounds
• CPC Class Codes: H01L 33/025 Physical imperfections, e.g. particular concentration or distribution of impurities
• CPC Class Codes: H01L 33/12 with a stress relaxation structure, e.g. buffer layer
• CPC Class Codes: H01L 33/20 with a particular shape, e.g. curved or truncated substrate
• CPC Class Codes: H01L 33/22 Roughened surfaces, e.g. at the interface between epitaxial layers

Abstract

A semiconductor light emitting diode having a textured structure and a method of manufacturing the same are provided. The semiconductor light emitting diode includes a first semiconductor layer formed into a textured structure, an intermediate layer formed between the textured structures of the patterned first semiconductor layer, and a second semiconductor layer, an active layer, and a third semiconductor layer sequentially formed on the first semiconductor layer and the intermediate layer.

Claims

1. A method of manufacturing a semiconductor light emitting diode having a textured structure, the method comprising:

forming a first semiconductor layer on a sapphire substrate;

exposing a portion of the sapphire substrate while forming the textured structure by etching the first semiconductor layer;

forming an intermediate layer on the exposed sapphire substrate between the textured structures of the first semiconductor layer; and

sequentially forming a second semiconductor layer, an active layer, and a third semiconductor layer on the first semiconductor layer and the intermediate layer.

2. The method of claim 1, wherein the exposing of a portion of the sapphire substrate while forming the textured structure by etching the first semiconductor layer comprises:

performing a first etching to form etch pits on the surface of the first semiconductor layer; and

performing a second etching to expose the surface of the sapphire substrate by etching the etch pits of the first semiconductor layer.

3. The method of claim 2, wherein the first etching is performed using H₃PO₄ and the second etching is performed using KOH.

4. The method of claim 1, wherein the forming of an intermediate layer on the exposed sapphire substrate between the textured structures of the first semiconductor layer comprises:

coating a transparent material on the exposed sapphire substrate between the textured structures of the first semiconductor layer; and

forming the intermediate layer by leveling the transparent material to expose the surface of the first semiconductor layer.

5. The method of claim 4, wherein the intermediate layer is formed of a transparent insulating material including at least one of SiO₂, SiN_x, Al₂O₃, HfO, TiO₂, or ZrO.

6. The method of claim 1, wherein the intermediate layer is formed of a transparent conductive material, such as ZnO or an In oxide that includes at least one additive selected from the group consisting of Mg, Ag, Zn, Sc, Hf, Zr, Te, Se, Ta, W, Nb, Cu, Si, Ni, Co, Mo, Cr, Mn, Hg, Pr, and La.

7. The method of claim 4, further comprising annealing after the transparent material is coated on the exposed sapphire substrate between the textured structures of the first semiconductor layer.

8. The method of claim 2, further comprising performing a third dry etching the exposed surface of the sapphire substrate.