LAYER TRANSFER PROCESS AND FUNCTIONALLY ENHANCED INTEGRATED CIRCUITS PRODUCED THEREBY

• US 20100081232A1
• Filed: 08/20/2009
• Published: 04/01/2010
• Est. Priority Date: 05/10/2007
• Status: Active Grant

• Current Assignee: LinkedIn Corporation (Microsoft Corporation)
• Original Assignee: International Business Machines Corporation
• Inventors: Purushothaman, Sampath, Furman, Bruce K., Sankarapandian, Muthumanickam, Topol, Anna
• Granted Patent: US 7,855,101 B2
• Time in Patent Office: Days
• US Class Current: 438/107
• CPC Class Codes: H01L 21/2007 Bonding of semiconductor wafers to insulating substrates or to semiconducting substrates using an intermediate insulating layer H01L21/2011 takes precedence; bonding of semiconductor wafers to semiconductor wafers for junction formation H01L21/187
• CPC Class Codes: H01L 21/768 Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
• CPC Class Codes: H01L 21/84 the substrate being other than a semiconductor body, e.g. being an insulating body
• CPC Class Codes: H01L 23/3735 Laminates or multilayers, e.g. direct bond copper ceramic substrates
• CPC Class Codes: H01L 27/0688 Integrated circuits having a three-dimensional layout
• CPC Class Codes: H01L 27/1203 the substrate comprising an insulating body on a semiconductor body, e.g. SOI three-dimensional layout H01L27/0688
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

A structure for a semiconductor components is provided having a device layer sandwiched on both sides by other active, passive, and interconnecting components. A wafer-level layer transfer process is used to create this planar (2D) IC structure with added functional enhancements.

Claims

1. A method of forming an integrated device structure comprising:

a) building a semiconductor device layer on a first substrate;

b) providing a set of first functional elements to connect at least some of the devices in said semiconductor device layer;

c) attaching a carrier substrate on top of said first functional elements;

d) removing said first substrate to expose the bottom side of the said semiconductor device layer;

e) building a set of second functional elements on said exposed bottom side of said semiconductor device layer including electrical connections to at least some of the devices in said semiconductor device layer;

f) attaching a foundation substrate to the exposed surface of said second functional elements;

g) removing said carrier substrate from the top of said second functional elements; and

h) providing input output connections on the exposed top surface of said second functional elements.

2. A method according to claim 1 wherein said first substrate is selected from the group consisting of silicon, silicon insulator, glass and quartz.

3. A method according to claim 1 wherein said first semiconductor device layer comprises devices made of a material selected from the group consisting of silicon, III-V compounds and II-VI compounds.

4. A method according to claim 1 wherein said first functional elements are selected from the group consisting of interconnect wiring, optical interconnects, microfluidic interconnects and a combination thereof.

5. A method according to claim 1 wherein said carrier substrate is made of a material selected from the group consisting of silicon, glass, quartz and ceramic.

6. A method according to claim 1 wherein said second set of functional elements are selected form the group consisting of interconnect wiring, power distribution wiring, ground planes, clock network wiring and optical interconnects.

7. A method according to claim 1 wherein said second set of functional elements further include means to provide heat dissipation and cooling to said semiconductor device layer.

8. A method according to claim 1 further comprising intermediate layers between said first and said second elements and said semiconductor device layer to provide attributes selected from the group consisting of durable adhesion and bonding, diffusion barrier function, passivation and combinations thereof.

9. A method according to claim 8 wherein said intermediate layers are selected from the group consisting of polyamic acid (PAA)-based polyimides, polyamic ester-based polyimides, pre-imidized polyimides, spin on glasses, silicon oxide, silicon nitride, silicon carbide, silicon carbonitride and combinations thereof.

10. A method of forming an integrated device structure comprising:

a) building a semiconductor device layer on a first substrate;

b) providing a set of first functional elements to connect at least some of the devices in said semiconductor device layer;

c) attaching a carrier substrate on top of said first functional elements;

d) removing said first substrate to expose the bottom side of the said semiconductor device layer;

e) building a set of second functional elements on said exposed bottom side of said semiconductor device layer including electrical connections to at least some of the devices in said semiconductor device layer;

f) attaching a foundation substrate to the exposed surface of said second functional elements;

g) partially thinning said carrier substrate;

h) building through vias and integrated elements in said thinned carrier substrate; and

i) providing input output means such as solder connections and microjoint connections on said thinned carrier substrate.

11. A method according to claim 10 wherein said first functional elements are selected from the group consisting of interconnect wiring, optical interconnects, microfluidic interconnects and a combination thereof.

12. A method according to claim 10 wherein said second set of functional elements further include means to provide heat dissipation and cooling to said semiconductor device layer.

13. A method according to claim 10 further comprising intermediate layers between said first and said second elements and said semiconductor device layer to provide attributes selected from the group consisting of durable adhesion and bonding, diffusion barrier function, passivation and combinations thereof.

14. A method according to claim 13 wherein said intermediate layers are selected from the group consisting of polyamic acid (PAA)-based polyimides, polyamic ester-based polyimides, pre-imidized polyimides, spin on glasses, silicon oxide, silicon nitride, silicon carbide, silicon carbonitride and combinations thereof.

15. A method of forming an integrated device structure comprising:

a) building a semiconductor device layer on a first substrate;

b) providing a set of first functional elements to connect at least some of the devices in said semiconductor device layer;

c) attaching a carrier substrate on top of said first functional elements;

d) removing said first substrate to expose the bottom side of said semiconductor device layer producing a first intermediate structure;

e) building a set of second functional elements on a foundation substrate to produce a second intermediate structure;

f) bonding said first and said second intermediate structures to form a third intermediate structure;

g) removing said carrier substrate, and

h) providing input output means on the exposed surface of said first functional elements to form said integrated device structure.

16. A method according to claims 15 wherein said first functional elements are selected from the group consisting of interconnect wiring, optical interconnects, microfluidic interconnects and a combination thereof.

17. A method according to claims 15 wherein said second set of functional elements further include means to provide heat dissipation and cooling to said semiconductor device layer.

18. A method according to claims 15 further comprising intermediate layers between said first and said second elements and said semiconductor device layer to provide attributes selected from the group consisting of durable adhesion and bonding, diffusion barrier function, passivation and combinations thereof.

19. A method according to claim 18 wherein said intermediate layers are selected from the group consisting of polyamic acid (PAA)-based polyimides, polyamic ester-based polyimides, pre-imidized polyimides, spin on glasses, silicon oxide, silicon nitride, silicon carbide, silicon carbonitride and combinations thereof.

20. A method of forming an integrated device structure comprising:

a) building a semiconductor device layer on a first substrate;

b) providing a set of first functional elements to connect at least some of the devices in said semiconductor device layer;

c) attaching a carrier substrate on top of said first functional elements;

d) removing said first substrate to expose the bottom side of the said semiconductor device layer producing a first intermediate structure;

e) building a set of second functional elements on a foundation substrate to produce a second intermediate structure;

f) bonding said first and said second intermediate structures to form a third intermediate structure;

g) partially thinning said carrier substrate;

h) building through vias and integrated passives elements in said thinned carrier substrate; and

i) providing input output means on said thinned carrier substrate to form said integrated device structure.

21. A method according to claim 20 wherein said first functional elements are selected from the group consisting of interconnect wiring, optical interconnects, microfluidic interconnects and a combination thereof.

22. A method according to claim 20 wherein said second set of functional elements are selected form the group consisting of interconnect wiring, power distribution wiring, ground planes, clock network wiring and optical interconnects.

23. A method according to claim 20 wherein said second set of functional elements further include means to provide heat dissipation and cooling to said semiconductor device layer.

24. A method according to claim 20 further comprising intermediate layers between said first and said second elements and said semiconductor device layer to provide attributes selected from the group consisting of durable adhesion and bonding, diffusion barrier function, passivation and combinations thereof.

25. A method according to claim 24 wherein said intermediate layers are selected from the group consisting of polyamic acid (PAA)-based polyimides, polyamic ester-based polyimides, pre-imidized polyimides, spin on glasses, silicon oxide, silicon nitride, silicon carbide, silicon carbonitride and combinations thereof.