Efficient Body Contact Field Effect Transistor with Reduced Body Resistance

• US 20100081239A1
• Filed: 10/01/2008
• Published: 04/01/2010
• Est. Priority Date: 10/01/2008
• Status: Active Grant

• Current Assignee: International Business Machines Corporation, NXP USA, Inc. (NXP Semiconductors NV)
• Original Assignee: International Business Machines Corporation
• Inventors: Min, Byoung W., Liang, Qingqing, Zollner, Stefan
• Granted Patent: US 7,820,530 B2
• Time in Patent Office: Days
• US Class Current: 438/151
• CPC Class Codes: H01L 21/26506 in group IV semiconductors
• CPC Class Codes: H01L 21/2658 of a molecular ion, e.g. decaborane
• CPC Class Codes: H01L 21/26586 characterised by the angle between the ion beam and the crystal planes or the main crystal surface
• CPC Class Codes: H01L 29/41758 for lateral devices with structured layout for source or drain region, i.e. the source or drain region having cellular, interdigitated or ring structure or being curved or angular H01L29/41733 - H01L29/4175 take precedence
• CPC Class Codes: H01L 29/4238 characterised by the surface lay-out
• CPC Class Codes: H01L 29/4983 with a lateral structure, e.g. a Polysilicon gate with a lateral doping variation or with a lateral composition variation or characterised by the sidewalls being composed of conductive, resistive or dielectric material
• CPC Class Codes: H01L 29/665 using self aligned silicidation, i.e. salicide formation of conductive layers comprising silicides H01L21/28518
• CPC Class Codes: H01L 29/6659 with both lightly doped source and drain extensions and source and drain self-aligned to the sides of the gate, e.g. lightly doped drain [LDD] MOSFET, double diffused drain [DDD] MOSFET
• CPC Class Codes: H01L 29/7833 with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's for thin film transistors H01L29/78618

Abstract

A method for forming a body contacted SOI transistor includes forming a semiconductor layer (103) having a body contact region (120), a body access region (121), and an active region (122). An SOI transistor is formed in the active region by etching a metal gate structure (107, 108) to have a first portion (130) formed over the active region, and a second portion (131) formed over at least part of the body access region. By implanting ions (203, 301) at a non-perpendicular angle into an implant region (204, 302) in the body access region so as to encroach toward the active region and/or under the second portion of the etched metal gate structure, silicide (306) may be subsequently formed over the body contact region and the implant region, thereby reducing formation of a depletion region (308) in the body access region.

Claims

1. A method for forming a body contacted semiconductor-on-insulator transistor comprising:

providing a first semiconductor layer over an insulating layer, where the first semiconductor layer comprises a body contact region, a body access region that is adjacent to the body contact region, and an active region that is adjacent to the body access region;

forming a semiconductor-on-insulator transistor in the active region by forming an etched metal gate structure over the first semiconductor layer, where the etched metal gate structure comprises;

a first portion formed over the active region with source and drain regions formed in the active region on opposite sides of the first portion, and

a second portion formed over at least part of the body access region;

implanting ions at a non-perpendicular angle into an implant region in the body access region to encroach under the second portion of the etched metal gate structure; and

forming silicide over the etched metal gate structure, the body contact region, and the implant region.

2. The method of claim 1, further comprising selectively forming a mask layer over part of the etched metal gate structure prior to implanting ions at a non-perpendicular angle, thereby exposing at least part of the second portion of the etched metal gate structure.

3. The method of claim 1, where providing a first semiconductor layer comprises providing a silicon layer over a buried oxide layer which is located on a silicon substrate layer.

4. The method of claim 1, where forming a semiconductor-on-insulator transistor comprises:

etching a gate stack comprising a high-k dielectric layer formed on the first semiconductor layer, a metal-based layer formed on the high-k dielectric layer, and a polysilicon layer formed on the metal-based layer to form the etched metal gate structure having exposed gate sidewalls;

forming sidewall spacers on the exposed gate sidewalls of the etched metal gate structure; and

implanting at least part of the source and drain regions in the active region using the etched metal gate structure and the sidewall spacers as an implant mask.

5. The method of claim 1, where implanting ions at a non-perpendicular angle comprises implanting dopant ions into at least a part of the second portion of the etched metal gate structure to counter-dope the second portion of the etched metal gate structure to have an opposite conductivity type from the first portion of the etched metal gate structure, thereby reducing formation of a depletion region in the body access region.

6. The method of claim 1, where implanting ions comprises selectively implanting heavy ions into the implant region at a non-perpendicular angle using an implant mask to protect the active region.

7. The method of claim 1, where implanting ions comprises selectively implanting dopant ions into the implant region at a non-perpendicular angle using an implant mask to protect the active region.

8. The method of claim 1, where implanting ions comprises implanting the implant region at a non-perpendicular angle with Xe, Ge, Ar, In, Sb, As, P, BF₂, Si, or another amorphizing ion, thereby amorphizing the implant region to encroach toward the active region.

9. The method of claim 1, further comprising partially recessing at least part of the body contact region and the body access region prior to forming silicide so that silicide is formed in the body access region to encroach under the second portion of the etched metal gate structure.

10. The method of claim 9, where partially recessing at least part of the body contact region and the body access region comprises:

selectively implanting at least part of the body contact region and the body access region to form an amorphized region; and

selectively etching the amorphized region to form a recess opening in the body contact region and the body access region, all prior to forming silicide over the etched metal gate structure, the body contact region, and the implant region.

11. A method of making a semiconductor device, comprising:

providing a substrate having a semiconductor layer and an insulating layer, wherein the semiconductor layer has a top surface and overlies the insulating layer;

doping an active region of the semiconductor layer to a first conductivity level;

doping a body access region of the semiconductor layer that is adjacent to the active region to a second conductivity level;

doping a body contact region of the semiconductor layer that is adjacent to the body access region to a third conductivity level;

forming a first gate insulating layer on the top surface;

forming a polysilicon gate layer over the first gate insulating layer;

selectively etching the polysilicon gate layer to form an etched gate structure having a first portion overlying the active region with source and drain regions formed in the active region on opposite sides of the first portion, and a second portion formed over at least part of the body access region;

implanting ions at a non-perpendicular angle into an implant region in the body access region to encroach under the second portion of the etched gate structure; and

forming silicide over the etched gate structure, the body contact region, and the implant region.

12. The method of claim 11, further comprising selectively forming a mask layer over part of the etched gate structure prior to implanting ions at a non-perpendicular angle, thereby exposing at least part of the second portion of the etched gate structure to implantation.

13. The method of claim 11, where implanting ions at a non-perpendicular angle comprises implanting dopant ions into at least a part of the second portion of the etched gate structure to counter-dope the second portion of the etched gate structure to have an opposite conductivity type from the first portion of the etched gate structure, thereby reducing formation of a depletion region in the body access region.

14. The method of claim 11, where implanting ions comprises selectively implanting heavy ions or dopant ions into the implant region at a non-perpendicular angle using an implant mask to protect the active region.

15. The method of claim 11, further comprising partially recessing at least part of the body contact region and the body access region prior to forming silicide so that silicide is formed in the body access region to encroach under the second portion of the etched gate structure.

16. The method of claim 15, where partially recessing at least part of the body contact region and the body access region comprises:

selectively implanting at least part of the body contact region and the body access region to form an amorphized region; and

selectively etching the amorphized region to form a recess opening in the body contact region and the body access region, all prior to forming silicide over the etched gate structure, the body contact region, and the implant region.

19. The method of claim 11, where implanting ions comprises selectively implanting heavy ions or dopant ions into the implant region at a non-perpendicular angle, thereby amorphizing the implant region to encroach toward the active region.

20. The method of claim 11, further comprising partially recessing at least part of the body contact region and the body access region prior to forming silicide so that silicide is formed in the body access region to encroach under the second portion of the etched metal gate electrode.

17. A method of forming a silicon-on-insulator transistor comprising:

forming an insulated substrate;

defining an active region in the insulated substrate which defines a location of the silicon-on-insulator transistor;

doping the active region to a first conductivity level;

doping a body access region of insulated substrate that is adjacent to the active region to a second conductivity level;

doping a body contact region of the insulated substrate that is adjacent to the body access region to a third conductivity level;

forming a high-k gate dielectric layer over the insulated substrate;

depositing and patterning a metal gate electrode comprising a metal-based layer and a polysilicon layer to define an etched metal gate electrode having a first portion overlying the active region, and a second portion formed over at least part of the body access region

forming sidewall spacers on the etched metal gate electrode to overlie at least part of the body access region;

forming source and drain regions in the active region on opposite sides of the first portion of the etched metal gate electrode;

implanting ions at a non-perpendicular angle into an implant region in the body access region to encroach under the second portion of the etched metal gate electrode; and

forming silicide over the etched metal gate electrode, the body contact region, and the implant region.

18. The method of claim 17, where implanting ions at a non-perpendicular angle comprises implanting dopant ions into at least a part of the second portion of the etched metal gate electrode to counter-dope the second portion of the etched metal gate electrode to have an opposite conductivity type from the first portion of the etched metal gate electrode, thereby reducing formation of a depletion region in the body access region.