METHODS FOR FABRICATING MOS DEVICES HAVING HIGHLY STRESSED CHANNELS

• US 20100081245A1
• Filed: 09/29/2008
• Published: 04/01/2010
• Est. Priority Date: 09/29/2008
• Status: Active Grant

• Current Assignee: Advanced Micro Devices, Inc.
• Original Assignee: Advanced Micro Devices, Inc.
• Inventors: YANG, Frank Bin, PAL, Rohit, HARGROVE, Michael J.
• Granted Patent: US 7,767,534 B2
• Time in Patent Office: Days
• US Class Current: 438/299
• CPC Class Codes: H01L 29/66636 with source or drain recessed by etching or first recessed by etching and then refilled
• CPC Class Codes: H01L 29/7847 using a memorization technique, e.g. re-crystallization under strain, bonding on a substrate having a thermal expansion coefficient different from the one of the region

Abstract

Methods for forming a semiconductor device comprising a silicon-comprising substrate are provided. One exemplary method comprises depositing a polysilicon layer overlying the silicon-comprising substrate, amorphizing the polysilicon layer, etching the amorphized polysilicon layer to form a gate electrode, depositing a stress-inducing layer overlying the gate electrode, annealing the silicon-comprising substrate to recrystallize the gate electrode, removing the stress-inducing layer, etching recesses into the substrate using the gate electrode as an etch mask, and epitaxially growing impurity-doped, silicon-comprising regions in the recesses.

Claims

1. A method for forming a semiconductor device comprising a silicon-comprising substrate, wherein the method comprises the steps of:

depositing a polysilicon layer overlying the silicon-comprising substrate;

amorphizing the polysilicon layer;

etching the amorphized polysilicon layer to form a gate electrode;

depositing a stress-inducing layer overlying the gate electrode;

annealing the silicon-comprising substrate to recrystallize the gate electrode;

removing the stress-inducing layer;

etching recesses into the substrate using the gate electrode as an etch mask; and

epitaxially growing impurity-doped, silicon-comprising regions in the recesses.

2. The method of claim 1, wherein the step of etching recesses is performed before the step of depositing a stress-inducing layer.

3. The method of claim 1, wherein the step of amorphizing the polysilicon layer comprises amorphizing the polysilicon layer with an ion implantation process.

4. The method of claim 1, wherein the step of depositing a stress-inducing layer comprises depositing a stress-inducing layer having a thickness in a range of from about 30 nm to about 70 nm.

5. The method of claim 1, wherein the step of depositing a stress-inducing layer comprises depositing a tensile stress-inducing silicon nitride layer.

6. The method of claim 1, wherein the step of depositing a stress-inducing layer comprises depositing a compressive stress-inducing silicon nitride layer.

7. The method of claim 1, wherein the step of epitaxially growing impurity-doped, silicon-comprising regions comprises epitaxially growing impurity-doped, silicon-comprising regions further comprising carbon or germanium.

8. The method of claim 1, wherein the step of etching recesses comprises etching recesses having a depth in a range of from about 50 nm to about 100 nm.

9. A method of fabricating an MOS transistor on and within a silicon-comprising substrate having a first surface, the method comprising the steps of:

depositing a polysilicon layer overlying the first surface of the silicon-comprising substrate;

amorphizing the polysilicon layer;

forming a gate stack comprising a gate electrode fabricated from the polysilicon layer and having sidewalls, the gate stack disposed overlying the first surface of the silicon-comprising substrate;

forming offset spacers adjacent the sidewalls of the gate electrode;

depositing a stress-inducing silicon nitride layer overlying the gate stack, the offset spacers, and the first surface;

annealing the silicon-comprising substrate;

removing the stress-inducing silicon nitride layer;

etching the first surface of the silicon-comprising substrate using the gate stack and the offset spacers as an etch mask to form recesses in the silicon-comprising substrate, the step of etching performed after the step of removing; and

epitaxially forming impurity-doped, silicon-comprising regions in the recesses.

10. The method of claim 9, wherein the step of depositing a stress-inducing silicon nitride layer comprises depositing a stress-inducing silicon nitride layer having a thickness in a range of from about 30 nm to about 70 nm.

11. The method of claim 9, wherein the step of depositing a stress-inducing silicon nitride layer comprises depositing a tensile stress-inducing silicon nitride layer.

12. The method of claim 9, wherein the step of depositing a stress-inducing silicon nitride layer comprises depositing a compressive stress-inducing silicon nitride layer.

13. The method of claim 9, wherein the step of etching the first surface of the silicon-comprising substrate comprises etching the first surface of the silicon-comprising substrate to form recesses having a depth in a range of from about 50 nm to about 100 nm.

14. The method of claim 9, wherein the step of epitaxially forming impurity-doped, silicon-comprising regions comprises epitaxially forming impurity-doped, silicon-comprising regions further comprising carbon or germanium.

15. A method of fabricating an MOS transistor on and within a silicon-comprising substrate having a first surface, the method comprising the steps of:

depositing a polysilicon layer overlying the first surface of the silicon-comprising substrate;

amorphizing the polysilicon layer;

forming a gate stack comprising a gate electrode fabricated from the polysilicon layer and having sidewalls, the gate stack disposed overlying the first surface of the silicon-comprising substrate;

forming offset spacers adjacent the sidewalls of the gate electrode;

etching the first surface of the silicon-comprising substrate using the gate stack and the offset spacers as an etch mask to form recesses in the silicon-comprising substrate, the recesses exposing second surfaces of the silicon-comprising substrate;

depositing a stress-inducing silicon nitride layer overlying the gate stack, the offset spacers, and the second surfaces;

annealing the silicon-comprising substrate;

removing the stress-inducing silicon nitride layer; and

epitaxially forming impurity-doped, silicon-comprising regions in the recesses.

16. The method of claim 15, wherein the step of depositing a stress-inducing silicon nitride layer comprises depositing a stress-inducing silicon nitride layer having a thickness in a range of from about 30 nm to about 70 nm.

17. The method of claim 15, wherein the step of depositing a stress-inducing silicon nitride layer comprises depositing a tensile stress-inducing silicon nitride layer.

18. The method of claim 15, wherein the step of depositing a stress-inducing silicon nitride layer comprises depositing a compressive stress-inducing silicon nitride layer.

19. The method of claim 15, wherein the step of etching the first surface comprises etching the first surface to form recesses having a depth in a range of from about 50 nm to about 100 nm.

20. The method of claim 15, wherein the step of epitaxially forming impurity-doped, silicon-comprising regions comprises epitaxially forming impurity-doped, silicon-comprising regions further comprising carbon or germanium.