MEMORY CELL OPERATION

• US 20100082884A1
• Filed: 02/18/2009
• Published: 04/01/2010
• Est. Priority Date: 09/26/2008
• Status: Active Grant

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micron Technology, Inc.
• Inventors: Chen, Liang (Leo), Chen, Frank
• Granted Patent: US 8,195,899 B2
• Time in Patent Office: Days
• US Class Current: 711/103
• CPC Class Codes: G06F 3/0604 Improving or facilitating administration, e.g. storage management
• CPC Class Codes: G06F 3/0688 Non-volatile semiconductor memory arrays
• CPC Class Codes: G11C 16/349 Arrangements for evaluating degradation, retention or wearout, e.g. by counting erase cycles
• CPC Class Codes: G11C 16/3495 Circuits or methods to detect or delay wearout of nonvolatile EPROM or EEPROM memory devices, e.g. by counting numbers of erase or reprogram cycles, by using multiple memory areas serially or cyclically

Abstract

The present disclosure includes memory devices and systems having memory cells, as well as methods for operating the memory cells. One or more methods for operating memory cells includes determining age information for a portion of the memory cells and communicating a command set for the portion of the memory cells, the command set including the age information.

Claims

1. A method for operating memory cells, comprising:

determining age information for a portion of the memory cells; and

communicating a command set for the portion of the memory cells,

wherein the command set includes the age information.

2. The method of claim 1, wherein communicating the command set includes transmitting at least one command cycle including the age information.

3. The method of claim 2, including providing the age information in a command cycle transmitted last in time.

4. The method of claim 2, wherein the command cycle transmitted last in time includes command-identifying information for the portion of the memory cells.

5. The method of claim 1, wherein communicating the command set includes transmitting at least one address cycle including the age information.

6. The method of claim 5, including providing the age information in an address cycle transmitted last in time.

7. The method of claim 6, wherein the address cycle transmitted last in time includes address-identifying information for the portion of the memory cells.

8. The method of claim 1, including determining at least one operating parameter for the portion of the memory cells at least partially in response to the age information.

9. The method of claim 1, wherein determining the at least one operating parameter is based, at least partially, on predetermined Vt drift curve information characterizing the performance of the memory cells.

10. A method for operating a memory device, comprising:

monitoring age information corresponding to an age of at least a particular portion of a memory device; and

communicating the age information to the memory device.

11. The method of claim 10, including switching the memory device between a safe operating mode and fast operating mode at least partially in response to the age information.

12. A method for operating a number of memory cells in a memory device, comprising:

determining a number of wear cycles performed on the number of memory cells;

determining a wear state based on the number of wear cycles; and

communicating access information for the number of memory cells from a memory access device to a memory, the access information including age information.

13. The method of claim 12, including determining at least one operating parameter for the number of memory cells at least partially in response to the age information.

14. The method of claim 13, including:

storing in the memory device, a data arrangement characterizing operating performance of the memory device, the data arrangement relating at least one operating parameter to age information; and

wherein determining the at least one operating parameter includes selecting from the data arrangement, a value of the at least one operating parameter or a change to the at least one operating parameter corresponding to the age information.

15. The method of claim 13, including:

storing in the memory device, a data arrangement characterizing operating performance of the memory device, the data arrangement relating at least one operating parameter to age information; and

wherein determining the at least one operating parameter includes executing a stored function to compute a value of the at least one operating parameter or compute a change to the at least one operating parameter corresponding to the age information.

16. The method of claim 13, wherein the at least one operating parameter is selected from a group including:

a programming pulse voltage magnitude, a programming pulse duration, a programming pulse frequency, and a quantity of programming pulses.

17. The method of claim 12, wherein the access information includes a command portion and an address portion, the address portion including identifying information and the age information corresponding to the number of memory cells.

18. The method of claim 17, wherein communicating the access information includes:

communicating a plurality of the address portion before the age information included in the cycle communicated last in time.

19. The method of claim 18, including representing the age information corresponding to the number of memory cells by one or more of the most significant bits of the cycle transmitted last in time.

20. The method of claim 19, wherein one or more of the least significant bits of the cycle communicated last in time represent a portion of the identifying information corresponding to the number of memory cells.

21. A memory device, comprising:

an array of memory cells; and

control circuitry coupled to the memory cells, and adapted to;

receive access information corresponding to a number of the memory cells;

retrieve age information from the access information; and

determine at least one operating parameter corresponding to the age information for the number of the memory cells at least partially in response to the age information.

22. The memory device of claim 21, wherein the age information is representative of a range of wear cycles performed on the number of memory cells.

23. The memory device of claim 21, wherein the control circuitry is adapted to determine a modification to an operating parameter.

24. The memory device of claim 21, wherein the control circuitry is adapted to store one or more bits of a last address cycle corresponding to retrieved age information in a register.

25. The memory device of claim 24, wherein the one or more bits are most significant bits of the last address cycle.

26. The memory device of claim 21, wherein the age information is information corresponding to a wear cycle quantity.

27. The memory device of claim 21, wherein the data arrangement characterizes a Vt drift curve for the memory device, relating the Vt curve to the age information.

28. The memory device of claim 21, wherein the at least one operating parameter is selected from a group including:

a programming pulse voltage magnitude, a programming pulse duration, a programming pulse frequency, and a quantity of programming pulses utilized.

29. The memory device of claim 21, wherein the age information indicates operating the number of the memory cells in a mode selected from a group including:

a high reliability mode and a high performance mode.

30. A memory system, comprising:

a memory access device;

a memory;

an interface coupled between the memory access device and the memory, the interface being configured to communicate a data arrangement that includes;

a first quantity of bits representing identifying information corresponding to a portion of the memory; and

a second quantity of bits representing age information corresponding to the portion of the memory,

wherein the first and second quantity of bits are communicated in N address cycles through the interface, the Nth address cycle including the second quantity of bits.

31. The memory system of claim 30, wherein the memory is a memory device.

32. The memory system of claim 30, wherein the second quantity of bits are one or more most significant bits of the Nth address cycle.

33. The memory system of claim 30, wherein a portion of the first quantity of bits are included in the Nth address cycle.