Flash Memory Controller For Electronic Data Flash Card

• US 20100082893A1
• Filed: 12/04/2009
• Published: 04/01/2010
• Est. Priority Date: 01/06/2000
• Status: Abandoned Application

• Current Assignee: Super Talent Electronics, Inc.
• Original Assignee: Super Talent Electronics, Inc.
• Inventors: Shen, Ming-Shiang, Ma, Abraham C., Lee, Edward W., Lee, Charles C., Yu, I-Kang
• Application Number:
  US12/631,761
• Publication Number:
  US 20100082893A1
• Time in Patent Office: Days
• US Class Current: 711/103
• CPC Class Codes: G06F 12/0246 in block erasable memory, e.g. flash memory
• CPC Class Codes: G06F 12/1416 by checking the object accessibility, e.g. type of access defined by the memory independently of subject rights G06F12/1458 takes precedence
• CPC Class Codes: G06F 21/32 using biometric data, e.g. fingerprints, iris scans or voiceprints
• CPC Class Codes: G06F 21/78 to assure secure storage of data address-based protection against unauthorised use of memory G06F12/14; record carriers for use with machines and with at least a part designed to carry digital markings G06K19/00
• CPC Class Codes: G06F 21/79 in semiconductor storage media, e.g. directly-addressable memories
• CPC Class Codes: G06K 19/07 with integrated circuit chips
• CPC Class Codes: G06K 19/07354 by biometrically sensitive means, e.g. fingerprint sensitive fingerprint sensors in general G06V40/12; biometrically activated access control G07C9/25
• CPC Class Codes: G06V 40/1365 Matching; Classification
• CPC Class Codes: G07C 9/257 electronically G07C9/26 takes precedence

Abstract

An electronic data flash card is accessible by a host computer, and includes a processing unit connected to a flash memory device that stores a data file, and an input-output interface circuit activated so as to establish a communication with the host computer. In an embodiment, the electronic data flash card uses a USB input/output interface circuit for communication with the host computer. A flash memory controller includes an index for converting logical addresses sent by the host computer into physical addresses associated with sectors of the flash memory device. The index is controlled by arbitration logic referencing to values from various look up tables and valid data stored in the flash memory device. The flash memory controller further includes a first-in-first-out unit (FIFO) for recycling obsolete sectors of the flash memory device in the background process so that they are available for reprogramming.

Claims

1. A storage system comprising:

a host computer including an interface bus; and

an electronic data flash card adapted to communicate with the host computer through a communication link established by the host computer over the interface bus, the electronic data flash card comprising;

a card body;

a flash memory device mounted on the card body, the flash memory device including a plurality of non-volatile memory cells for storing a data file, the memory cells being arranged in at least one of a plurality of memory blocks, and a plurality of pages, and a plurality of sectors, wherein the flash memory device comprises one of a Multi-Level Cell flash memory device and a Single Level Cell flash memory device;

an input/output interface circuit mounted on the card body for establishing communication with the host computer, wherein the input/output interface circuit includes a Universal Serial Bus (USB) interface circuit including means for transmitting said data file using a USB mass-storage class protocol; and

a flash memory controller mounted on the card body and electrically connected to the flash memory device and the input/output interface circuit, wherein the flash memory controller comprises;

(a) means for determining whether the flash memory device is supported by a processing unit of the flash memory controller;

(b) an index for storing a plurality of logical addresses and a plurality of physical addresses such that each physical address is assigned to an associated logical address, where each physical address corresponds to an associated plurality of memory cells of the flash memory device, and wherein the index comprises at least one look-up-table (LUT) for storing the logical addresses and the associated physical addresses, each LUT including static random access memory (SRAM) cells;

(c) means for operating in one of;

a data writing mode in which the flash memory controller activates the input/output interface circuit to receive the data file from the host computer, and to store the data file in a physical address of the flash memory device associated with a logical address and transfer length received with a standard USB write command issued from the host computer to the flash memory controller;

a data retrieving mode in which the flash memory controller receives a standard USB read command issued from the host computer including the logical address and transfer length, and activates the input/output interface circuit to transmit the data file read from the physical address of the flash memory device associated with the logical address to the host computer; and

a data resetting mode in which data from one or more memory cells is erased from the flash memory device, wherein the data resetting mode is initiated and performed by the flash memory controller after receiving the standard USB write command using arbitration logic and data that is stored on the flash memory device;

(d) a read-only memory (ROM) for storing boot code (BC) that provides initial executing sequences for the processor unit to initialize the flash memory controller; and

(e) a SRAM for storing look-up-tables (LUT) for translation of a logical address from the host computer and a flash physical address for the data writing mode and the retrieving mode operations,

wherein the flash memory controller further comprises means for assigning each the physical address to its associated the logical address,

wherein the flash memory device includes a multiple flash memory devices,

wherein the flash memory controller includes means for supporting at least one of multi-channel parallel access and interleave access to the multiple flash memory devices, and

wherein the card body comprises a substrate on which the non-volatile memory device, the input/output interface circuit, and the flash memory controller are mounted using integrated circuits packaging technology.

2. An electronic data flash card adapted to be accessed by a host computer that is capable of establishing a communication link, the electronic data flash card comprising:

a card body;

a flash memory device mounted on the card body, the flash memory device including a plurality of non-volatile memory cells for storing a data file, the memory cells being arranged in at least one of a plurality of memory blocks, and a plurality of pages, and a plurality of sectors, wherein the flash memory device comprises one of a Multi-Level Cell flash memory device and a Single Level Cell flash memory device;

an input/output interface circuit mounted on the card body for establishing communication with the host computer, wherein the input/output interface circuit includes a Universal Serial Bus (USB) interface circuit including means for transmitting said data file using a USB mass-storage class protocol; and

a flash memory controller mounted on the card body and electrically connected to the flash memory device and the input/output interface circuit, wherein the flash memory controller comprises;

(a) means for determining whether the flash memory device is supported by a processing unit of the flash memory controller;

(b) an index for storing a plurality of logical addresses and a plurality of physical addresses such that each physical address is assigned to an associated logical address, where each physical address corresponds to an associated plurality of memory cells of the flash memory device, and wherein the index comprises at least one look-up-table (LUT) for storing the logical addresses and the associated physical addresses, each LUT including static random access memory (SRAM) cells;

(c) means for operating in one of;

a data writing mode in which the flash memory controller activates the input/output interface circuit to receive the data file from the host computer, and to store the data file in a physical address of the flash memory device associated with a logical address and transfer length received with a standard USB write command issued from the host computer to the flash memory controller;

a data retrieving mode in which the flash memory controller receives a standard USB read command issued from the host computer including the logical address and transfer length, and activates the input/output interface circuit to transmit the data file read from the physical address of the flash memory device associated with the logical address to the host computer; and

a data resetting mode in which data from one or more memory cells is erased from the flash memory device, wherein the data resetting mode is initiated and performed by the flash memory controller after receiving the standard USB write command using arbitration logic and data that is stored on the flash memory device;

(d) a read-only memory (ROM) for storing boot code (BC) that provides initial executing sequences for the processor unit to initialize the flash memory controller; and

(e) a SRAM for storing look-up-tables (LUT) for translation of a logical address from the host computer and a flash physical address for the data writing mode and the retrieving mode operations,

wherein the flash memory device includes a multiple flash memory devices,

wherein the flash memory controller includes means for supporting at least one of multi-channel parallel access and interleave access to the multiple flash memory devices, and

wherein the card body comprises a substrate on which the non-volatile memory device, the input/output interface circuit, and the flash memory controller are mounted using integrated circuits packaging technology.

3. An electronic data flash card adapted to be accessed by a host computer that is capable of establishing a communication link, the electronic data flash card comprising:

a card body;

a flash memory device mounted on the card body, the flash memory device including a plurality of non-volatile memory cells for storing a data file, the memory cells being arranged in at least one of a plurality of memory blocks, and a plurality of pages, and a plurality of sectors, wherein the flash memory device comprises one of a Multi-Level Cell flash memory device and a Single Level Cell flash memory device;

an input/output interface circuit mounted on the card body for establishing communication with the host computer, wherein the input/output interface circuit includes a Universal Serial Bus (USB) interface circuit including means for transmitting said data file using a USB mass-storage class protocol; and

a flash memory controller mounted on the card body and electrically connected to the flash memory device and the input/output interface circuit, wherein the flash memory controller comprises;

(a) means for determining whether the flash memory device is supported by a processing unit of the flash memory controller;

(b) an index for storing a plurality of logical addresses and a plurality of physical addresses such that each physical address is assigned to an associated logical address, where each physical address corresponds to an associated plurality of memory cells of the flash memory device, and wherein the index comprises at least one look-up-table (LUT) for storing the logical addresses and the associated physical addresses, each LUT including static random access memory (SRAM) cells;

(c) means for operating in one of;

a data writing mode in which the flash memory controller activates the input/output interface circuit to receive the data file from the host computer, and to store the data file in a physical address of the flash memory device associated with a logical address and transfer length received with a standard USB write command issued from the host computer to the flash memory controller;

a data retrieving mode in which the flash memory controller receives a standard USB read command issued from the host computer including the logical address and transfer length, and activates the input/output interface circuit to transmit the data file read from the physical address of the flash memory device associated with the logical address to the host computer; and

a data resetting mode in which data from one or more memory cells is erased from the flash memory device, wherein the data resetting mode is initiated and performed by the flash memory controller after receiving the standard USB write command using arbitration logic and data that is stored on the flash memory device;

(d) a read-only memory (ROM) for storing boot code (BC) that provides initial executing sequences for the processor unit to initialize the flash memory controller;

wherein the flash memory device includes a multiple flash memory devices,

wherein the flash memory controller includes means for supporting at least one of multi-channel parallel access and interleave access to the multiple flash memory devices, and

wherein the card body comprises a substrate on which the non-volatile memory device, the input/output interface circuit, and the flash memory controller are mounted using integrated circuits packaging technology.

4. A flash memory controller for an electronic data flash card adapted to be accessed by a host computer that is capable of establishing a communication link, the electronic data flash card including:

a card body;

a flash memory device mounted on the card body, the flash memory device including a plurality of non-volatile memory cells for storing a data file, the memory cells being arranged in at least one of a plurality of memory blocks, and a plurality of pages, and a plurality of sectors, wherein the flash memory device comprises one of a Multi-Level Cell flash memory device and a Single Level Cell flash memory device;

an input/output interface circuit mounted on the card body for establishing communication with the host computer, wherein the input/output interface circuit includes a Universal Serial Bus (USB) interface circuit including means for transmitting said data file using a USB protocol; and

a flash memory controller mounted on the card body and electrically connected to the flash memory device and the input/output interface circuit,

wherein the card body comprises a substrate on which the non-volatile memory device, the input/output interface circuit, and the flash memory controller are mounted using integrated circuits packaging technology, and

wherein the flash memory controller comprises;

(a) means for determining whether the flash memory device is supported by a processing unit of the flash memory controller;

(b) an index for storing a plurality of logical addresses and a plurality of physical addresses such that each physical address is assigned to an associated logical address, where each physical address corresponds to an associated plurality of memory cells of the flash memory device, and wherein the index comprises at least one look-up-table (LUT) for storing the logical addresses and the associated physical addresses, each LUT including static random access memory (SRAM) cells;

(c) means for operating in one of;

a data writing mode in which the flash memory controller activates the input/output interface circuit to receive the data file from the host computer, and to store the data file in a physical address of the flash memory device associated with a logical address and transfer length received with a standard USB write command issued from the host computer to the flash memory controller;

a data retrieving mode in which the flash memory controller receives a standard USB read command issued from the host computer including the logical address and transfer length, and activates the input/output interface circuit to transmit the data file read from the physical address of the flash memory device associated with the logical address to the host computer; and

a data resetting mode in which data from one or more memory cells is erased from the flash memory device, wherein the data resetting mode is initiated and performed by the flash memory controller after receiving the standard USB write command using arbitration logic and data that is stored on the flash memory device; and

(d) a read-only memory (ROM) for storing boot code (BC) that provides initial executing sequences for the processor unit to initialize the flash memory controller,

wherein the flash memory device includes a multiple flash memory devices, and

wherein the flash memory controller includes means for supporting at least one of multi-channel parallel access and interleave access to the multiple flash memory devices.

5. A method for managing a flash memory device in an electronic data flash card adapted to be accessed by a host computer that is capable of establishing a communication link, the electronic data flash card including:

a card body;

a flash memory device mounted on the card body, the flash memory device including a plurality of non-volatile memory cells for storing a data file, the memory cells being arranged in at least one of a plurality of memory blocks, and a plurality of pages, and a plurality of sectors, wherein the flash memory device comprises one of a Multi-Level Cell flash memory device and a Single Level Cell flash memory device;

an input/output interface circuit mounted on the card body for establishing communication with the host computer, wherein the input/output interface circuit includes a Universal Serial Bus (USB) interface circuit including means for transmitting said data file using a USB mass-storage class protocol; and

a flash memory controller mounted on the card body and electrically connected to the flash memory device and the input/output interface circuit,

wherein the card body comprises a substrate on which the non-volatile memory device, the input/output interface circuit, and the flash memory controller are mounted using integrated circuits packaging technology, and

wherein the method comprises;

(a) determining whether the flash memory device is supported by a processing unit of the flash memory controller;

(b) storing a plurality of logical addresses and a plurality of physical addresses in an index such that each physical address is assigned to an associated logical address, where each physical address corresponds to an associated plurality of memory cells of the flash memory device, and wherein the index comprises at least one look-up-table (LUT) for storing the logical addresses and the associated physical addresses, each LUT including static random access memory (SRAM) cells;

(c) operating in one of;

a data writing mode in which the flash memory controller activates the input/output interface circuit to receive the data file from the host computer, and to store the data file in a physical address of the flash memory device associated with a logical address and transfer length received with a standard USB write command issued from the host computer to the flash memory controller;

a data retrieving mode in which the flash memory controller receives a standard USB read command issued from the host computer including the logical address and transfer length, and activates the input/output interface circuit to transmit the data file read from the physical address of the flash memory device associated with the logical address to the host computer; and

a data resetting mode in which data from one or more memory cells is erased from the flash memory device, wherein the data resetting mode is initiated and performed by the flash memory controller after receiving the standard USB write command using arbitration logic and data that is stored on the flash memory device; and

(d) storing boot code (BC) in a read-only memory (ROM) that provides initial executing sequences for the processor unit to initialize the flash memory controller,

wherein the flash memory device includes a multiple flash memory devices, and

wherein the flash memory controller includes means for supporting at least one of multi-channel parallel access and interleave access to the multiple flash memory devices.

6. A computer readable medium for managing a flash memory device in an electronic data flash card adapted to be accessed by a host computer that is capable of establishing a communication link, the electronic data flash card including:

a card body;

a flash memory device mounted on the card body, the flash memory device including a plurality of non-volatile memory cells for storing a data file, the memory cells being arranged in at least one of a plurality of memory blocks, and a plurality of pages, and a plurality of sectors, wherein the flash memory device comprises one of a Multi-Level Cell flash memory device and a Single Level Cell flash memory device;

an input/output interface circuit mounted on the card body for establishing communication with the host computer, wherein the input/output interface circuit includes a Universal Serial Bus (USB) interface circuit including means for transmitting said data file using a USB mass-storage class protocol; and

a flash memory controller mounted on the card body and electrically connected to the flash memory device and the input/output interface circuit,

wherein the card body comprises a substrate on which the non-volatile memory device, the input/output interface circuit, and the flash memory controller are mounted using integrated circuits packaging technology, and

wherein the computer readable medium contain program instructions which, when executed by the flash memory controller, cause the electronic data flash card to execute a method comprising;

(a) determining whether the flash memory device is supported by a processing unit of the flash memory controller;

(b) storing a plurality of logical addresses and a plurality of physical addresses in an index such that each physical address is assigned to an associated logical address, where each physical address corresponds to an associated plurality of memory cells of the flash memory device, and wherein the index comprises at least one look-up-table (LUT) for storing the logical addresses and the associated physical addresses, each LUT including static random access memory (SRAM) cells;

(c) operating in one of;

a data writing mode in which the flash memory controller activates the input/output interface circuit to receive the data file from the host computer, and to store the data file in a physical address of the flash memory device associated with a logical address and transfer length received with a standard USB write command issued from the host computer to the flash memory controller;

a data retrieving mode in which the flash memory controller receives a standard USB read command issued from the host computer including the logical address and transfer length, and activates the input/output interface circuit to transmit the data file read from the physical address of the flash memory device associated with the logical address to the host computer; and

a data resetting mode in which data from one or more memory cells is erased from the flash memory device, wherein the data resetting mode is initiated and performed by the flash memory controller after receiving the standard USB write command using arbitration logic and data that is stored on the flash memory device; and

(d) storing boot code (BC) in a read-only memory (ROM) that provides initial executing sequences for the processor unit to initialize the flash memory controller,

wherein the flash memory device includes a multiple flash memory devices, and

wherein the flash memory controller includes means for supporting at least one of multi-channel parallel access and interleave access to the multiple flash memory devices.

7. A storage system comprising:

a host computer including an host computer link; and

a single chip electronic data flash card system adapted to communicate with the host computer through the host computer link, the single chip electronic data flash card system comprising;

a card reader including connected between the host computer link and a card reader interface bus, and

a single chip data electronic flash card, wherein the single chip data electronic flash card comprises;

a card body;

a flash memory device mounted on the card body, the flash memory device including a plurality of non-volatile memory cells for storing a data file, the memory cells being arranged in at least one of a plurality of memory blocks, and a plurality of pages, and a plurality of sectors, wherein the flash memory device comprises one of a Multi-Level Cell flash memory device and a Single Level Cell flash memory device;

a card reader interface circuit mounted on the card body for establishing communication with the host computer by way of the card reader, wherein the card reader interface circuit includes a Universal Serial Bus (USB) interface circuit including means for transmitting said data file using a USB mass-storage class protocol over said card reader interface bus; and

a flash memory controller mounted on the card body and electrically connected to the flash memory device and the card reader interface circuit, wherein the flash memory controller comprises;

(a) means for determining whether the flash memory device is supported by a processing unit of the flash memory controller;

(b) an index for storing a plurality of logical addresses and a plurality of physical addresses such that each physical address is assigned to an associated logical address, where each physical address corresponds to an associated plurality of memory cells of the flash memory device, and wherein the index comprises at least one look-up-table (LUT) for storing the logical addresses and the associated physical addresses, each LUT including static random access memory (SRAM) cells;

(c) means for operating in one of;

a data writing mode in which the flash memory controller activates the card reader interface circuit to receive the data file from the host computer by way of the card reader, and to store the data file in a physical address of the flash memory device associated with a logical address and transfer length received with a standard USB write command issued from the host computer to the flash memory controller;

a data retrieving mode in which the flash memory controller receives a standard USB read command issued from the host computer including the logical address and transfer length, and activates the card reader interface circuit to transmit the data file read from the physical address of the flash memory device associated with the logical address to the host computer by way of the card reader; and

a data resetting mode in which data from one or more memory cells is erased from the flash memory device, wherein the data resetting mode is initiated and performed by the flash memory controller after receiving the standard USB write command using arbitration logic and data that is stored on the flash memory device;

(d) a read-only memory (ROM) for storing boot code (BC) that provides initial executing sequences for the processor unit to initialize the flash memory controller; and

(e) a SRAM for storing look-up-tables (LUT) for translation of a logical address from the host computer and a flash physical address for the data writing mode and the retrieving mode operations,

wherein the card body comprises a substrate on which the non-volatile memory device, the card reader interface circuit, and the flash memory controller are mounted using integrated circuits packaging technology such that the non-volatile memory device, the card reader interface circuit and the flash memory controller are integrated into one integrated circuit package,

wherein the card reader interface bus comprises one of a Secure Digital interface circuit, a MultiMedia Card interface circuit, and

wherein the host computer link comprises a Universal Serial Bus circuit.

8. A single chip electronic data flash card system adapted to be accessed by a host computer that is capable of establishing a host communication link, the single chip electronic data flash card system comprising:

a card reader including connected between the host computer link and a card reader interface bus, and

a single chip data electronic flash card, wherein the single chip data electronic flash card comprises;

a card body;

a flash memory device mounted on the card body, the flash memory device including a plurality of non-volatile memory cells for storing a data file, the memory cells being arranged in at least one of a plurality of memory blocks, and a plurality of pages, and a plurality of sectors, wherein the flash memory device comprises one of a Multi-Level Cell flash memory device and a Single Level Cell flash memory device;

a card reader interface circuit mounted on the card body for establishing communication with the host computer by way of the card reader,

wherein the card reader interface circuit includes a Universal Serial Bus (USB) interface circuit including means for transmitting said data file using a USB mass-storage class protocol over said card reader interface bus; and

a flash memory controller mounted on the card body and electrically connected to the flash memory device and the card reader interface circuit, wherein the flash memory controller comprises;

(a) means for determining whether the flash memory device is supported by a processing unit of the flash memory controller;

(b) an index for storing a plurality of logical addresses and a plurality of physical addresses such that each physical address is assigned to an associated logical address, where each physical address corresponds to an associated plurality of memory cells of the flash memory device, and wherein the index comprises at least one look-up-table (LUT) for storing the logical addresses and the associated physical addresses, each LUT including static random access memory (SRAM) cells;

(c) means for operating in one of;

a data writing mode in which the flash memory controller activates the card reader interface circuit to receive the data file from the host computer by way of the card reader, and to store the data file in a physical address of the flash memory device associated with a logical address and transfer length received with a standard USB write command issued from the host computer to the flash memory controller;

a data retrieving mode in which the flash memory controller receives a standard USB read command issued from the host computer including the logical address and transfer length, and activates the card reader interface circuit to transmit the data file read from the physical address of the flash memory device associated with the logical address to the host computer by way of the card reader; and

a data resetting mode in which data from one or more memory cells is erased from the flash memory device, wherein the data resetting mode is initiated and performed by the flash memory controller after receiving the standard USB write command using arbitration logic and data that is stored on the flash memory device;

(d) a read-only memory (ROM) for storing boot code (BC) that provides initial executing sequences for the processor unit to initialize the flash memory controller; and

(e) a SRAM for storing look-up-tables (LUT) for translation of a logical address from the host computer and a flash physical address for the data writing mode and the retrieving mode operations,

wherein the card body comprises a substrate on which the non-volatile memory device, the card reader interface circuit, and the flash memory controller are mounted using integrated circuits packaging technology such that the non-volatile memory device, the card reader interface circuit and the flash memory controller are integrated into one integrated circuit package,

wherein the card reader interface bus comprises one of a Secure Digital interface circuit, a MultiMedia Card interface circuit, and

wherein the host computer link comprises a Universal Serial Bus circuit.

9. A storage system comprising:

a host computer including an host computer link; and

a single chip electronic data flash card system adapted to communicate with the host computer through the host computer link, the single chip electronic data flash card system comprising;

a card reader including connected between the host computer link and a card reader interface bus, and

a single chip data electronic flash card, wherein the single chip data electronic flash card comprises;

a card body;

a flash memory device mounted on the card body, the flash memory device including a plurality of non-volatile memory cells for storing a data file, the memory cells being arranged in at least one of a plurality of memory blocks, and a plurality of pages, and a plurality of sectors, wherein the flash memory device comprises one of a Multi-Level Cell flash memory device and a Single Level Cell flash memory device;

a card reader interface circuit mounted on the card body for establishing communication with the host computer by way of the card reader, wherein the card reader interface circuit includes a Secure Digital (SD) interface circuit including means for transmitting said data file using a SD protocol over said card reader interface bus; and

a flash memory controller mounted on the card body and electrically connected to the flash memory device and the card reader interface circuit, wherein the flash memory controller comprises;

(a) means for determining whether the flash memory device is supported by a processing unit of the flash memory controller;

(b) an index for storing a plurality of logical addresses and a plurality of physical addresses such that each physical address is assigned to an associated logical address, where each physical address corresponds to an associated plurality of memory cells of the flash memory device, and wherein the index comprises at least one look-up-table (LUT) for storing the logical addresses and the associated physical addresses, each LUT including static random access memory (SRAM) cells;

(c) means for operating in one of;

a data writing mode in which the flash memory controller activates the card reader interface circuit to receive the data file from the host computer by way of the card reader, and to store the data file in a physical address of the flash memory device associated with a logical address and transfer length received with a standard SD write command issued from the host computer to the flash memory controller;

a data retrieving mode in which the flash memory controller receives a standard SD read command issued from the host computer including the logical address and transfer length, and activates the card reader interface circuit to transmit the data file read from the physical address of the flash memory device associated with the logical address to the host computer by way of the card reader; and

a data resetting mode in which data from one or more memory cells is erased from the flash memory device, wherein the data resetting mode is initiated and performed by the flash memory controller after receiving the standard SD write command using arbitration logic and data that is stored on the flash memory device;

(d) a read-only memory (ROM) for storing boot code (BC) that provides initial executing sequences for the processor unit to initialize the flash memory controller; and

(e) a SRAM for storing look-up-tables (LUT) for translation of a logical address from the host computer and a flash physical address for the data writing mode and the retrieving mode operations,

wherein the card body comprises a substrate on which the non-volatile memory device, the card reader interface circuit, and the flash memory controller are mounted using integrated circuits packaging technology such that the non-volatile memory device, the card reader interface circuit and the flash memory controller are integrated into one integrated circuit package,

wherein the card reader interface bus comprises a Secure Digital interface circuit, and

wherein the host computer link comprises a Secure Digital interface circuit.

10. A single chip electronic data flash card system adapted to be accessed by a host computer that is capable of establishing a host computer link, the single chip electronic data flash card system comprising:

a card reader including connected between the host computer link and a card reader interface bus, and

a single chip data electronic flash card, wherein the single chip data electronic flash card comprises;

a card body;

a flash memory device mounted on the card body, the flash memory device including

a plurality of non-volatile memory cells for storing a data file, the memory cells being arranged in at least one of a plurality of memory blocks, and a plurality of pages, and a plurality of sectors, wherein the flash memory device comprises one of a Multi-Level Cell flash memory device and a Single Level Cell flash memory device;

a card reader interface circuit mounted on the card body for establishing communication with the host computer by way of the card reader, wherein the card reader interface circuit includes a Secure Digital (SD) interface circuit including means for transmitting said data file using a SD protocol over said card reader interface bus; and

a flash memory controller mounted on the card body and electrically connected to the flash memory device and the card reader interface circuit, wherein the flash memory controller comprises;

(a) means for determining whether the flash memory device is supported by a processing unit of the flash memory controller;

(b) an index for storing a plurality of logical addresses and a plurality of physical addresses such that each physical address is assigned to an associated logical address, where each physical address corresponds to an associated plurality of memory cells of the flash memory device, and wherein the index comprises at least one look-up-table (LUT) for storing the logical addresses and the associated physical addresses, each LUT including static random access memory (SRAM) cells;

(c) means for operating in one of;

a data writing mode in which the flash memory controller activates the card reader interface circuit to receive the data file from the host computer by way of the card reader, and to store the data file in a physical address of the flash memory device associated with a logical address and transfer length received with a standard SD write command issued from the host computer to the flash memory controller;

a data retrieving mode in which the flash memory controller receives a standard SD read command issued from the host computer including the logical address and transfer length, and activates the card reader interface circuit to transmit the data file read from the physical address of the flash memory device associated with the logical address to the host computer by way of the card reader; and

a data resetting mode in which data from one or more memory cells is erased from the flash memory device, wherein the data resetting mode is initiated and performed by the flash memory controller after receiving the standard SD write command using arbitration logic and data that is stored on the flash memory device;

(d) a read-only memory (ROM) for storing boot code (BC) that provides initial executing sequences for the processor unit to initialize the flash memory controller; and

(e) a SRAM for storing look-up-tables (LUT) for translation of a logical address from the host computer and a flash physical address for the data writing mode and the retrieving mode operations,

wherein the card body comprises a substrate on which the non-volatile memory device, the card reader interface circuit, and the flash memory controller are mounted using integrated circuits packaging technology such that the non-volatile memory device, the card reader interface circuit and the flash memory controller are integrated into one integrated circuit package,

wherein the card reader interface circuit comprises a Secure Digital interface circuit, and wherein the host computer link comprises a Secure Digital interface circuit.

11. A single chip electronic data flash card accessed by a card reader that is capable of establishing a communication link through a card reader interface circuit, wherein the single chip data electronic flash card comprises:

a card body;

a flash memory device mounted on the card body, the flash memory device including a plurality of non-volatile memory cells for storing a data file, the memory cells being arranged in at least one of a plurality of memory blocks, and a plurality of pages, and a plurality of sectors, wherein the flash memory device comprises one of a Multi-Level Cell flash memory device and a Single Level Cell flash memory device;

a card reader interface circuit mounted on the card body for establishing communication with the host computer by way of the card reader, wherein the card reader interface circuit includes a Secure Digital (SD) interface circuit including means for transmitting said data file using a SD protocol over said card reader interface bus; and

a flash memory controller mounted on the card body and electrically connected to the flash memory device and the card reader interface circuit, wherein the flash memory controller comprises;

(a) means for determining whether the flash memory device is supported by a processing unit of the flash memory controller;

(b) an index for storing a plurality of logical addresses and a plurality of physical addresses such that each physical address is assigned to an associated logical address, where each physical address corresponds to an associated plurality of memory cells of the flash memory device, and wherein the index comprises at least one look-up-table (LUT) for storing the logical addresses and the associated physical addresses, each LUT including static random access memory (SRAM) cells;

(c) means for operating in one of;

a data writing mode in which the flash memory controller activates the card reader interface circuit to receive the data file from the host computer by way of the card reader, and to store the data file in a physical address of the flash memory device associated with a logical address and transfer length received with a standard SD write command issued from the host computer to the flash memory controller;

a data retrieving mode in which the flash memory controller receives a standard SD read command issued from the host computer including the logical address and transfer length, and activates the card reader interface circuit to transmit the data file read from the physical address of the flash memory device associated with the logical address to the host computer by way of the card reader; and

a data resetting mode in which data from one or more memory cells is erased from the flash memory device, wherein the data resetting mode is initiated and performed by the flash memory controller after receiving the standard SD write command using arbitration logic and data that is stored on the flash memory device;

(d) a read-only memory (ROM) for storing boot code (BC) that provides initial executing sequences for the processor unit to initialize the flash memory controller; and

(e) a SRAM for storing look-up-tables (LUT) for translation of a logical address from the host computer and a flash physical address for the data writing mode and the retrieving mode operations,

wherein the card body comprises a substrate on which the non-volatile memory device, the card reader interface circuit, and the flash memory controller are mounted using integrated circuits packaging technology such that the non-volatile memory device, the card reader interface circuit and the flash memory controller are integrated into one integrated circuit package, and

wherein the card reader interface circuit comprises one of a Secure Digital interface circuit, and a MultiMedia Card interface circuit.

12. A method for managing a flash memory device in a single chip electronic data flash card adapted to be accessed by a card reader that is capable of establishing a communication link through a card reader interface circuit, wherein the single chip electronic data flash card includes:

a card body;

a flash memory device mounted on the card body, the flash memory device including a plurality of non-volatile memory cells for storing a data file, the memory cells being arranged in at least one of a plurality of memory blocks, and a plurality of pages, and a plurality of sectors, wherein the flash memory device comprises one of a Multi-Level Cell flash memory device and a Single Level Cell flash memory device;

a card reader interface circuit mounted on the card body for establishing communication with the host computer, wherein the card reader interface circuit includes a Secure Digital interface circuit including means for transmitting said data file using a protocol; and

a flash memory controller mounted on the card body and electrically connected to the flash memory device and the card reader interface circuit,

wherein the card body comprises a substrate on which the non-volatile memory device, the card reader interface circuit, and the flash memory controller are mounted using integrated circuits packaging technology, and

wherein the method comprises;

(a) determining whether the flash memory device is supported by a processing unit of the flash memory controller;

(b) storing a plurality of logical addresses and a plurality of physical addresses in an index such that each physical address is assigned to an associated logical address, where each physical address corresponds to an associated plurality of memory cells of the flash memory device, and wherein the index comprises at least one look-up-table (LUT) for storing the logical addresses and the associated physical addresses, each LUT including static random access memory (SRAM) cells;

(c) operating in one of;

a data writing mode in which the flash memory controller activates the card reader interface circuit to receive the data file from the host computer, and to store the data file in a physical address of the flash memory device associated with a logical address and transfer length received with a standard SD write command issued from the host computer to the flash memory controller;

a data retrieving mode in which the flash memory controller receives a standard SD read command issued from the host computer including the logical address and transfer length, and activates the card reader interface circuit to transmit the data file read from the physical address of the flash memory device associated with the logical address to the host computer; and

a data resetting mode in which data from one or more memory cells is erased from the flash memory device, wherein the data resetting mode is initiated and performed by the flash memory controller after receiving the standard SD write command using arbitration logic and data that is stored on the flash memory device; and

(d) storing boot code (BC) in a read-only memory (ROM) that provides initial executing sequences for the processor unit to initialize the flash memory controller,

wherein the card body comprises a substrate on which the non-volatile memory device, the card reader interface circuit, and the flash memory controller are mounted using integrated circuits packaging technology such that the non-volatile memory device, the card reader interface circuit and the flash memory controller are integrated into one integrated circuit package, and

wherein the card reader interface circuit comprises one of a Secure Digital interface circuit, and a MultiMedia Card interface circuit.

13. A computer readable medium for managing a flash memory device in a single chip electronic data flash card adapted to be accessed by a card reader that is capable of establishing a communication link through card reader, wherein the single chip electronic data flash card includes:

a card body;

a flash memory device mounted on the card body, the flash memory device including a plurality of non-volatile memory cells for storing a data file, the memory cells being arranged in at least one of a plurality of memory blocks, and a plurality of pages, and a plurality of sectors, wherein the flash memory device comprises one of a Multi-Level Cell flash memory device and a Single Level Cell flash memory device; and

a card reader interface circuit mounted on the card body for establishing communication with the host computer, wherein the card reader interface circuit includes a micro Secure Digital (SD) interface circuit including means for transmitting said data file using a SD protocol; and

a flash memory controller mounted on the card body and electrically connected to the flash memory device and the card reader interface circuit,

wherein the card body comprises a substrate on which the non-volatile memory device, the card reader interface circuit, and the flash memory controller are mounted using integrated circuits packaging technology, and

wherein the computer readable medium contain program instructions which, when executed by the flash memory controller, cause the electronic data flash card to execute a method comprising;

(a) determining whether the flash memory device is supported by a processing unit of the flash memory controller;

(b) storing a plurality of logical addresses and a plurality of physical addresses in an index such that each physical address is assigned to an associated logical address, where each physical address corresponds to an associated plurality of memory cells of the flash memory device, and wherein the index comprises at least one look-up-table (LUT) for storing the logical addresses and the associated physical addresses, each LUT including static random access memory (SRAM) cells;

(c) operating in one of;

a data writing mode in which the flash memory controller activates the card reader interface circuit to receive the data file from the host computer, and to store the data file in a physical address of the flash memory device associated with a logical address and transfer length received with a standard SD write command issued from the host computer to the flash memory controller;

a data retrieving mode in which the flash memory controller receives a standard SD read command issued from the host computer including the logical address and transfer length, and activates the card reader interface circuit to transmit the data file read from the physical address of the flash memory device associated with the logical address to the host computer; and

a data resetting mode in which data from one or more memory cells is erased from the flash memory device, wherein the data resetting mode is initiated and performed by the flash memory controller after receiving the standard SD write command using arbitration logic and data that is stored on the flash memory device; and

(d) storing boot code (BC) in a read-only memory (ROM) that provides initial executing sequences for the processor unit to initialize the flash memory controller,

wherein the card body comprises a substrate on which the non-volatile memory device, the card reader interface circuit, and the flash memory controller are mounted using integrated circuits packaging technology such that the non-volatile memory device, the card reader interface circuit and the flash memory controller are integrated into one integrated circuit package, and

wherein the card reader interface circuit comprises one of a Secure Digital interface circuit, and a MultiMedia Card interface circuit.