DELEGATED VIRTUALIZATION ACROSS PHYSICAL PARTITIONS OF A MULTI-CORE PROCESSOR (MCP)

• US 20100082938A1
• Filed: 09/30/2008
• Published: 04/01/2010
• Est. Priority Date: 09/30/2008
• Status: Active Grant

• Current Assignee: Kyndryl Incorporated
• Original Assignee: International Business Machines Corporation
• Inventors: Hofstee, Harm P., Kim, Moon J., Kim, Daeik, Duvalsaint, Karl J.
• Granted Patent: US 8,341,638 B2
• Time in Patent Office: Days
• US Class Current: 712/13
• CPC Class Codes: G06F 2209/483 Multiproc
• CPC Class Codes: G06F 9/4893 taking into account power or heat criteria power management in computers in general G06F1/3203; thermal management in computers in general G06F1/206
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

This disclosure describes an apparatus, computer architecture, method, operating system, compiler, and application program products for MPEs as well as virtualization across physical boundaries that define physical partitions in a symmetric MCP. Among other things, the disclosure is applied to a generic microprocessor architecture with a set (e.g., one or more) of controlling/main processing elements (e.g., MPEs) and a set of groups of sub-processing elements (e.g., SPEs). The arrangement also enables MPEs to delegate functionality to one or more groups of SPEs such that those group(s) of SPEs may act as pseudo MPEs. Such delegation may occur across the physical boundaries. Regardless, the pseudo MPEs may utilize pseudo virtualized control threads to control the behavior of other groups of SPEs also across physical boundaries.

Claims

1. A multi-core processor, comprising:

a first physical partition comprising a first main processing element;

a second physical partition comprising a second main processing element and a group of sub-processing elements, the group of sub processing elements being designated as a pseudo main processing element by the first main processing element in the first physical partition;

a logical partition of sub-processing elements; and

a pseudo virtualized control thread associating the pseudo main processing element of the second physical partition with the logical partition of sub-processing elements.

2. The multi-core processor of claim 1, the logical partition of sub-processing elements being in the first physical partition.

3. The multi-core processor of claim 1, the logical partition of sub-processing elements being in the second physical partition.

4. The multi-core processor of claim 1, the logical partition of sub-processing elements being in a third physical partition.

5. The multi-core processor of claim 1, the pseudo virtualized control thread being configured to send program code and data to the sub-processing elements of the logical partition.

6. The multi-core processor of claim 1, pseudo virtualized control thread being further configured to collect computation results from the sub-processing elements of the logical partition.

7. The multi-core processor of claim 1, pseduo virtualized control thread controlling a clock speed, power consumption and computation loading of the sub-processing elements of the first logical partition.

8. A processing method, comprising:

delegating a set of functions of a main processing element in a first physical partition of a multi-core processor to a group of sub-processing elements in a second physical partition of the multi-core processor to cause the group of sub-processing elements to act as a pseudo main processing element;

associating the pseudo main processing element with a logical partition of sub-processing elements using a set of pseudo virtualized control threads; and

controlling the logical partition of sub-processing elements using the set of pseudo virtualized control threads.

10. The processing method of claim 10, the logical partition of sub-processing elements being in the second physical partition.

9. The processing method of claim 10, the logical partition of sub-processing elements being in the first physical partition.

13. The processing method of claim 10, the logical partition of sub-processing elements being in a third physical partition.

14. The processing method of claim 10, the pseudo virtualized control thread being configured to send program code and data to the sub-processing elements of the logical partition.

15. The processing method of claim 10, the pseudo virtualized control thread being further configured to collect computation results from the sub-processing elements of the logical partition.

16. The processing method of claim 10, the pseduo virtualized control thread controlling a clock speed, power consumption and computation loading of the sub-processing elements of the first logical partition.

17. A multi-core processor, comprising:

a first physical partition comprising a first main processing element;

a second physical partition comprising a second main processing element and a group of sub-processing elements, the group of sub processing elements being designated as a pseudo main processing element by the first main processing element in the first physical partition;

a logical partition of sub-processing elements;

in at least one of the first physical partition and a third physical partition in the multi-core processor; and

a pseudo virtualized control thread associating the pseudo main processing element of the second physical partition with the logical partition of sub-processing elements.

18. A method for deploying a processing system:

providing a multi-core processor being configured to;

delegate a set of functions of a main processing element in a first physical partition of the multi-core processor to a group of sub-processing elements in a second physical partition of the multi-core processor to cause the group of sub-processing elements to act as a pseudo main processing element;

associate the pseudo main processing element with a logical partition of sub-processing elements using a set of pseudo virtualized control threads; and

control the logical partition of sub-processing elements using the set of pseudo virtualized control threads.

19. The method of claim 18, the logical partition of sub-processing elements being in the first physical partition.

20. The method of claim 18, the logical partition of sub-processing elements being in the second physical partition.

21. The method of claim 18, the logical partition of sub-processing elements being in a third physical partition.